1//===-- RISCVInstrInfoA.td - RISC-V 'A' instructions -------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the RISC-V instructions from the standard 'A', Atomic
11// Instructions extension.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Instruction class templates
17//===----------------------------------------------------------------------===//
18
19let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
20class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
21    : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
22                    (outs GPR:$rd), (ins GPR:$rs1),
23                    opcodestr, "$rd, (${rs1})"> {
24  let rs2 = 0;
25}
26
27multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
28  def ""     : LR_r<0, 0, funct3, opcodestr>;
29  def _AQ    : LR_r<1, 0, funct3, opcodestr # ".aq">;
30  def _RL    : LR_r<0, 1, funct3, opcodestr # ".rl">;
31  def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
32}
33
34let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
35class AMO_rr<bits<5> funct5, bit aq, bit rl, bits<3> funct3, string opcodestr>
36    : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
37                    (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
38                    opcodestr, "$rd, $rs2, (${rs1})">;
39
40multiclass AMO_rr_aq_rl<bits<5> funct5, bits<3> funct3, string opcodestr> {
41  def ""     : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
42  def _AQ    : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
43  def _RL    : AMO_rr<funct5, 0, 1, funct3, opcodestr # ".rl">;
44  def _AQ_RL : AMO_rr<funct5, 1, 1, funct3, opcodestr # ".aqrl">;
45}
46
47//===----------------------------------------------------------------------===//
48// Instructions
49//===----------------------------------------------------------------------===//
50
51let Predicates = [HasStdExtA] in {
52defm LR_W       : LR_r_aq_rl<0b010, "lr.w">;
53defm SC_W       : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
54defm AMOSWAP_W  : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
55defm AMOADD_W   : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
56defm AMOXOR_W   : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
57defm AMOAND_W   : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
58defm AMOOR_W    : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
59defm AMOMIN_W   : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
60defm AMOMAX_W   : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
61defm AMOMINU_W  : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
62defm AMOMAXU_W  : AMO_rr_aq_rl<0b11100, 0b010, "amomaxu.w">;
63} // Predicates = [HasStdExtA]
64
65let Predicates = [HasStdExtA, IsRV64] in {
66defm LR_D       : LR_r_aq_rl<0b011, "lr.d">;
67defm SC_D       : AMO_rr_aq_rl<0b00011, 0b011, "sc.d">;
68defm AMOSWAP_D  : AMO_rr_aq_rl<0b00001, 0b011, "amoswap.d">;
69defm AMOADD_D   : AMO_rr_aq_rl<0b00000, 0b011, "amoadd.d">;
70defm AMOXOR_D   : AMO_rr_aq_rl<0b00100, 0b011, "amoxor.d">;
71defm AMOAND_D   : AMO_rr_aq_rl<0b01100, 0b011, "amoand.d">;
72defm AMOOR_D    : AMO_rr_aq_rl<0b01000, 0b011, "amoor.d">;
73defm AMOMIN_D   : AMO_rr_aq_rl<0b10000, 0b011, "amomin.d">;
74defm AMOMAX_D   : AMO_rr_aq_rl<0b10100, 0b011, "amomax.d">;
75defm AMOMINU_D  : AMO_rr_aq_rl<0b11000, 0b011, "amominu.d">;
76defm AMOMAXU_D  : AMO_rr_aq_rl<0b11100, 0b011, "amomaxu.d">;
77} // Predicates = [HasStedExtA, IsRV64]
78
79//===----------------------------------------------------------------------===//
80// Pseudo-instructions and codegen patterns
81//===----------------------------------------------------------------------===//
82
83let Predicates = [HasStdExtA] in {
84
85/// Atomic loads and stores
86
87// Fences will be inserted for atomic load/stores according to the logic in
88// RISCVTargetLowering::{emitLeadingFence,emitTrailingFence}.
89
90defm : LdPat<atomic_load_8,  LB>;
91defm : LdPat<atomic_load_16, LH>;
92defm : LdPat<atomic_load_32, LW>;
93
94defm : StPat<atomic_store_8,  SB, GPR>;
95defm : StPat<atomic_store_16,  SH, GPR>;
96defm : StPat<atomic_store_32, SW, GPR>;
97} // Predicates = [HasStdExtF]
98