1 //===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H 11 #define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H 12 13 #include "llvm/Support/DataTypes.h" 14 15 #include <memory> 16 17 namespace llvm { 18 19 class MCAsmBackend; 20 class MCCodeEmitter; 21 class MCContext; 22 class MCInstrInfo; 23 class MCObjectTargetWriter; 24 class MCRegisterInfo; 25 class MCSubtargetInfo; 26 class MCTargetOptions; 27 class StringRef; 28 class Target; 29 class Triple; 30 class raw_pwrite_stream; 31 class raw_ostream; 32 33 Target &getTheSystemZTarget(); 34 35 namespace SystemZMC { 36 // How many bytes are in the ABI-defined, caller-allocated part of 37 // a stack frame. 38 const int64_t CallFrameSize = 160; 39 40 // The offset of the DWARF CFA from the incoming stack pointer. 41 const int64_t CFAOffsetFromInitialSP = CallFrameSize; 42 43 // Maps of asm register numbers to LLVM register numbers, with 0 indicating 44 // an invalid register. In principle we could use 32-bit and 64-bit register 45 // classes directly, provided that we relegated the GPR allocation order 46 // in SystemZRegisterInfo.td to an AltOrder and left the default order 47 // as %r0-%r15. It seems better to provide the same interface for 48 // all classes though. 49 extern const unsigned GR32Regs[16]; 50 extern const unsigned GRH32Regs[16]; 51 extern const unsigned GR64Regs[16]; 52 extern const unsigned GR128Regs[16]; 53 extern const unsigned FP32Regs[16]; 54 extern const unsigned FP64Regs[16]; 55 extern const unsigned FP128Regs[16]; 56 extern const unsigned VR32Regs[32]; 57 extern const unsigned VR64Regs[32]; 58 extern const unsigned VR128Regs[32]; 59 extern const unsigned AR32Regs[16]; 60 extern const unsigned CR64Regs[16]; 61 62 // Return the 0-based number of the first architectural register that 63 // contains the given LLVM register. E.g. R1D -> 1. 64 unsigned getFirstReg(unsigned Reg); 65 66 // Return the given register as a GR64. getRegAsGR64(unsigned Reg)67inline unsigned getRegAsGR64(unsigned Reg) { 68 return GR64Regs[getFirstReg(Reg)]; 69 } 70 71 // Return the given register as a low GR32. getRegAsGR32(unsigned Reg)72inline unsigned getRegAsGR32(unsigned Reg) { 73 return GR32Regs[getFirstReg(Reg)]; 74 } 75 76 // Return the given register as a high GR32. getRegAsGRH32(unsigned Reg)77inline unsigned getRegAsGRH32(unsigned Reg) { 78 return GRH32Regs[getFirstReg(Reg)]; 79 } 80 81 // Return the given register as a VR128. getRegAsVR128(unsigned Reg)82inline unsigned getRegAsVR128(unsigned Reg) { 83 return VR128Regs[getFirstReg(Reg)]; 84 } 85 } // end namespace SystemZMC 86 87 MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII, 88 const MCRegisterInfo &MRI, 89 MCContext &Ctx); 90 91 MCAsmBackend *createSystemZMCAsmBackend(const Target &T, 92 const MCSubtargetInfo &STI, 93 const MCRegisterInfo &MRI, 94 const MCTargetOptions &Options); 95 96 std::unique_ptr<MCObjectTargetWriter> createSystemZObjectWriter(uint8_t OSABI); 97 } // end namespace llvm 98 99 // Defines symbolic names for SystemZ registers. 100 // This defines a mapping from register name to register number. 101 #define GET_REGINFO_ENUM 102 #include "SystemZGenRegisterInfo.inc" 103 104 // Defines symbolic names for the SystemZ instructions. 105 #define GET_INSTRINFO_ENUM 106 #include "SystemZGenInstrInfo.inc" 107 108 #define GET_SUBTARGETINFO_ENUM 109 #include "SystemZGenSubtargetInfo.inc" 110 111 #endif 112