1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
17 
18 #include "SystemZ.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 
23 namespace llvm {
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26   FIRST_NUMBER = ISD::BUILTIN_OP_END,
27 
28   // Return with a flag operand.  Operand 0 is the chain operand.
29   RET_FLAG,
30 
31   // Calls a function.  Operand 0 is the chain operand and operand 1
32   // is the target address.  The arguments start at operand 2.
33   // There is an optional glue operand at the end.
34   CALL,
35   SIBCALL,
36 
37   // TLS calls.  Like regular calls, except operand 1 is the TLS symbol.
38   // (The call target is implicitly __tls_get_offset.)
39   TLS_GDCALL,
40   TLS_LDCALL,
41 
42   // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43   // accesses (LARL).  Operand 0 is the address.
44   PCREL_WRAPPER,
45 
46   // Used in cases where an offset is applied to a TargetGlobalAddress.
47   // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48   // PCREL_WRAPPER for an anchor point.  This is used so that we can
49   // cheaply refer to either the full address or the anchor point
50   // as a register base.
51   PCREL_OFFSET,
52 
53   // Integer absolute.
54   IABS,
55 
56   // Integer comparisons.  There are three operands: the two values
57   // to compare, and an integer of type SystemZICMP.
58   ICMP,
59 
60   // Floating-point comparisons.  The two operands are the values to compare.
61   FCMP,
62 
63   // Test under mask.  The first operand is ANDed with the second operand
64   // and the condition codes are set on the result.  The third operand is
65   // a boolean that is true if the condition codes need to distinguish
66   // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67   // register forms do but the memory forms don't).
68   TM,
69 
70   // Branches if a condition is true.  Operand 0 is the chain operand;
71   // operand 1 is the 4-bit condition-code mask, with bit N in
72   // big-endian order meaning "branch if CC=N"; operand 2 is the
73   // target block and operand 3 is the flag operand.
74   BR_CCMASK,
75 
76   // Selects between operand 0 and operand 1.  Operand 2 is the
77   // mask of condition-code values for which operand 0 should be
78   // chosen over operand 1; it has the same form as BR_CCMASK.
79   // Operand 3 is the flag operand.
80   SELECT_CCMASK,
81 
82   // Evaluates to the gap between the stack pointer and the
83   // base of the dynamically-allocatable area.
84   ADJDYNALLOC,
85 
86   // Count number of bits set in operand 0 per byte.
87   POPCNT,
88 
89   // Wrappers around the ISD opcodes of the same name.  The output is GR128.
90   // Input operands may be GR64 or GR32, depending on the instruction.
91   SMUL_LOHI,
92   UMUL_LOHI,
93   SDIVREM,
94   UDIVREM,
95 
96   // Add/subtract with overflow/carry.  These have the same operands as
97   // the corresponding standard operations, except with the carry flag
98   // replaced by a condition code value.
99   SADDO, SSUBO, UADDO, USUBO, ADDCARRY, SUBCARRY,
100 
101   // Set the condition code from a boolean value in operand 0.
102   // Operand 1 is a mask of all condition-code values that may result of this
103   // operation, operand 2 is a mask of condition-code values that may result
104   // if the boolean is true.
105   // Note that this operation is always optimized away, we will never
106   // generate any code for it.
107   GET_CCMASK,
108 
109   // Use a series of MVCs to copy bytes from one memory location to another.
110   // The operands are:
111   // - the target address
112   // - the source address
113   // - the constant length
114   //
115   // This isn't a memory opcode because we'd need to attach two
116   // MachineMemOperands rather than one.
117   MVC,
118 
119   // Like MVC, but implemented as a loop that handles X*256 bytes
120   // followed by straight-line code to handle the rest (if any).
121   // The value of X is passed as an additional operand.
122   MVC_LOOP,
123 
124   // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
125   NC,
126   NC_LOOP,
127   OC,
128   OC_LOOP,
129   XC,
130   XC_LOOP,
131 
132   // Use CLC to compare two blocks of memory, with the same comments
133   // as for MVC and MVC_LOOP.
134   CLC,
135   CLC_LOOP,
136 
137   // Use an MVST-based sequence to implement stpcpy().
138   STPCPY,
139 
140   // Use a CLST-based sequence to implement strcmp().  The two input operands
141   // are the addresses of the strings to compare.
142   STRCMP,
143 
144   // Use an SRST-based sequence to search a block of memory.  The first
145   // operand is the end address, the second is the start, and the third
146   // is the character to search for.  CC is set to 1 on success and 2
147   // on failure.
148   SEARCH_STRING,
149 
150   // Store the CC value in bits 29 and 28 of an integer.
151   IPM,
152 
153   // Compiler barrier only; generate a no-op.
154   MEMBARRIER,
155 
156   // Transaction begin.  The first operand is the chain, the second
157   // the TDB pointer, and the third the immediate control field.
158   // Returns CC value and chain.
159   TBEGIN,
160   TBEGIN_NOFLOAT,
161 
162   // Transaction end.  Just the chain operand.  Returns CC value and chain.
163   TEND,
164 
165   // Create a vector constant by filling byte N of the result with bit
166   // 15-N of the single operand.
167   BYTE_MASK,
168 
169   // Create a vector constant by replicating an element-sized RISBG-style mask.
170   // The first operand specifies the starting set bit and the second operand
171   // specifies the ending set bit.  Both operands count from the MSB of the
172   // element.
173   ROTATE_MASK,
174 
175   // Replicate a GPR scalar value into all elements of a vector.
176   REPLICATE,
177 
178   // Create a vector from two i64 GPRs.
179   JOIN_DWORDS,
180 
181   // Replicate one element of a vector into all elements.  The first operand
182   // is the vector and the second is the index of the element to replicate.
183   SPLAT,
184 
185   // Interleave elements from the high half of operand 0 and the high half
186   // of operand 1.
187   MERGE_HIGH,
188 
189   // Likewise for the low halves.
190   MERGE_LOW,
191 
192   // Concatenate the vectors in the first two operands, shift them left
193   // by the third operand, and take the first half of the result.
194   SHL_DOUBLE,
195 
196   // Take one element of the first v2i64 operand and the one element of
197   // the second v2i64 operand and concatenate them to form a v2i64 result.
198   // The third operand is a 4-bit value of the form 0A0B, where A and B
199   // are the element selectors for the first operand and second operands
200   // respectively.
201   PERMUTE_DWORDS,
202 
203   // Perform a general vector permute on vector operands 0 and 1.
204   // Each byte of operand 2 controls the corresponding byte of the result,
205   // in the same way as a byte-level VECTOR_SHUFFLE mask.
206   PERMUTE,
207 
208   // Pack vector operands 0 and 1 into a single vector with half-sized elements.
209   PACK,
210 
211   // Likewise, but saturate the result and set CC.  PACKS_CC does signed
212   // saturation and PACKLS_CC does unsigned saturation.
213   PACKS_CC,
214   PACKLS_CC,
215 
216   // Unpack the first half of vector operand 0 into double-sized elements.
217   // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
218   UNPACK_HIGH,
219   UNPACKL_HIGH,
220 
221   // Likewise for the second half.
222   UNPACK_LOW,
223   UNPACKL_LOW,
224 
225   // Shift each element of vector operand 0 by the number of bits specified
226   // by scalar operand 1.
227   VSHL_BY_SCALAR,
228   VSRL_BY_SCALAR,
229   VSRA_BY_SCALAR,
230 
231   // For each element of the output type, sum across all sub-elements of
232   // operand 0 belonging to the corresponding element, and add in the
233   // rightmost sub-element of the corresponding element of operand 1.
234   VSUM,
235 
236   // Compare integer vector operands 0 and 1 to produce the usual 0/-1
237   // vector result.  VICMPE is for equality, VICMPH for "signed greater than"
238   // and VICMPHL for "unsigned greater than".
239   VICMPE,
240   VICMPH,
241   VICMPHL,
242 
243   // Likewise, but also set the condition codes on the result.
244   VICMPES,
245   VICMPHS,
246   VICMPHLS,
247 
248   // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
249   // vector result.  VFCMPE is for "ordered and equal", VFCMPH for "ordered and
250   // greater than" and VFCMPHE for "ordered and greater than or equal to".
251   VFCMPE,
252   VFCMPH,
253   VFCMPHE,
254 
255   // Likewise, but also set the condition codes on the result.
256   VFCMPES,
257   VFCMPHS,
258   VFCMPHES,
259 
260   // Test floating-point data class for vectors.
261   VFTCI,
262 
263   // Extend the even f32 elements of vector operand 0 to produce a vector
264   // of f64 elements.
265   VEXTEND,
266 
267   // Round the f64 elements of vector operand 0 to f32s and store them in the
268   // even elements of the result.
269   VROUND,
270 
271   // AND the two vector operands together and set CC based on the result.
272   VTM,
273 
274   // String operations that set CC as a side-effect.
275   VFAE_CC,
276   VFAEZ_CC,
277   VFEE_CC,
278   VFEEZ_CC,
279   VFENE_CC,
280   VFENEZ_CC,
281   VISTR_CC,
282   VSTRC_CC,
283   VSTRCZ_CC,
284 
285   // Test Data Class.
286   //
287   // Operand 0: the value to test
288   // Operand 1: the bit mask
289   TDC,
290 
291   // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
292   // ATOMIC_LOAD_<op>.
293   //
294   // Operand 0: the address of the containing 32-bit-aligned field
295   // Operand 1: the second operand of <op>, in the high bits of an i32
296   //            for everything except ATOMIC_SWAPW
297   // Operand 2: how many bits to rotate the i32 left to bring the first
298   //            operand into the high bits
299   // Operand 3: the negative of operand 2, for rotating the other way
300   // Operand 4: the width of the field in bits (8 or 16)
301   ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
302   ATOMIC_LOADW_ADD,
303   ATOMIC_LOADW_SUB,
304   ATOMIC_LOADW_AND,
305   ATOMIC_LOADW_OR,
306   ATOMIC_LOADW_XOR,
307   ATOMIC_LOADW_NAND,
308   ATOMIC_LOADW_MIN,
309   ATOMIC_LOADW_MAX,
310   ATOMIC_LOADW_UMIN,
311   ATOMIC_LOADW_UMAX,
312 
313   // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
314   //
315   // Operand 0: the address of the containing 32-bit-aligned field
316   // Operand 1: the compare value, in the low bits of an i32
317   // Operand 2: the swap value, in the low bits of an i32
318   // Operand 3: how many bits to rotate the i32 left to bring the first
319   //            operand into the high bits
320   // Operand 4: the negative of operand 2, for rotating the other way
321   // Operand 5: the width of the field in bits (8 or 16)
322   ATOMIC_CMP_SWAPW,
323 
324   // Atomic compare-and-swap returning CC value.
325   // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
326   ATOMIC_CMP_SWAP,
327 
328   // 128-bit atomic load.
329   // Val, OUTCHAIN = ATOMIC_LOAD_128(INCHAIN, ptr)
330   ATOMIC_LOAD_128,
331 
332   // 128-bit atomic store.
333   // OUTCHAIN = ATOMIC_STORE_128(INCHAIN, val, ptr)
334   ATOMIC_STORE_128,
335 
336   // 128-bit atomic compare-and-swap.
337   // Val, CC, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap)
338   ATOMIC_CMP_SWAP_128,
339 
340   // Byte swapping load.
341   //
342   // Operand 0: the address to load from
343   // Operand 1: the type of load (i16, i32, i64)
344   LRV,
345 
346   // Byte swapping store.
347   //
348   // Operand 0: the value to store
349   // Operand 1: the address to store to
350   // Operand 2: the type of store (i16, i32, i64)
351   STRV,
352 
353   // Prefetch from the second operand using the 4-bit control code in
354   // the first operand.  The code is 1 for a load prefetch and 2 for
355   // a store prefetch.
356   PREFETCH
357 };
358 
359 // Return true if OPCODE is some kind of PC-relative address.
isPCREL(unsigned Opcode)360 inline bool isPCREL(unsigned Opcode) {
361   return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
362 }
363 } // end namespace SystemZISD
364 
365 namespace SystemZICMP {
366 // Describes whether an integer comparison needs to be signed or unsigned,
367 // or whether either type is OK.
368 enum {
369   Any,
370   UnsignedOnly,
371   SignedOnly
372 };
373 } // end namespace SystemZICMP
374 
375 class SystemZSubtarget;
376 class SystemZTargetMachine;
377 
378 class SystemZTargetLowering : public TargetLowering {
379 public:
380   explicit SystemZTargetLowering(const TargetMachine &TM,
381                                  const SystemZSubtarget &STI);
382 
383   // Override TargetLowering.
getScalarShiftAmountTy(const DataLayout &,EVT)384   MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
385     return MVT::i32;
386   }
getVectorIdxTy(const DataLayout & DL)387   MVT getVectorIdxTy(const DataLayout &DL) const override {
388     // Only the lower 12 bits of an element index are used, so we don't
389     // want to clobber the upper 32 bits of a GPR unnecessarily.
390     return MVT::i32;
391   }
getPreferredVectorAction(EVT VT)392   TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
393     const override {
394     // Widen subvectors to the full width rather than promoting integer
395     // elements.  This is better because:
396     //
397     // (a) it means that we can handle the ABI for passing and returning
398     //     sub-128 vectors without having to handle them as legal types.
399     //
400     // (b) we don't have instructions to extend on load and truncate on store,
401     //     so promoting the integers is less efficient.
402     //
403     // (c) there are no multiplication instructions for the widest integer
404     //     type (v2i64).
405     if (VT.getScalarSizeInBits() % 8 == 0)
406       return TypeWidenVector;
407     return TargetLoweringBase::getPreferredVectorAction(VT);
408   }
409   EVT getSetCCResultType(const DataLayout &DL, LLVMContext &,
410                          EVT) const override;
411   bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
412   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
413   bool isLegalICmpImmediate(int64_t Imm) const override;
414   bool isLegalAddImmediate(int64_t Imm) const override;
415   bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
416                              unsigned AS,
417                              Instruction *I = nullptr) const override;
418   bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
419                                       unsigned Align,
420                                       bool *Fast) const override;
421   bool isTruncateFree(Type *, Type *) const override;
422   bool isTruncateFree(EVT, EVT) const override;
423   const char *getTargetNodeName(unsigned Opcode) const override;
424   std::pair<unsigned, const TargetRegisterClass *>
425   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
426                                StringRef Constraint, MVT VT) const override;
427   TargetLowering::ConstraintType
428   getConstraintType(StringRef Constraint) const override;
429   TargetLowering::ConstraintWeight
430     getSingleConstraintMatchWeight(AsmOperandInfo &info,
431                                    const char *constraint) const override;
432   void LowerAsmOperandForConstraint(SDValue Op,
433                                     std::string &Constraint,
434                                     std::vector<SDValue> &Ops,
435                                     SelectionDAG &DAG) const override;
436 
getInlineAsmMemConstraint(StringRef ConstraintCode)437   unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
438     if (ConstraintCode.size() == 1) {
439       switch(ConstraintCode[0]) {
440       default:
441         break;
442       case 'o':
443         return InlineAsm::Constraint_o;
444       case 'Q':
445         return InlineAsm::Constraint_Q;
446       case 'R':
447         return InlineAsm::Constraint_R;
448       case 'S':
449         return InlineAsm::Constraint_S;
450       case 'T':
451         return InlineAsm::Constraint_T;
452       }
453     }
454     return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
455   }
456 
457   /// If a physical register, this returns the register that receives the
458   /// exception address on entry to an EH pad.
459   unsigned
getExceptionPointerRegister(const Constant * PersonalityFn)460   getExceptionPointerRegister(const Constant *PersonalityFn) const override {
461     return SystemZ::R6D;
462   }
463 
464   /// If a physical register, this returns the register that receives the
465   /// exception typeid on entry to a landing pad.
466   unsigned
getExceptionSelectorRegister(const Constant * PersonalityFn)467   getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
468     return SystemZ::R7D;
469   }
470 
471   /// Override to support customized stack guard loading.
useLoadStackGuardNode()472   bool useLoadStackGuardNode() const override {
473     return true;
474   }
insertSSPDeclarations(Module & M)475   void insertSSPDeclarations(Module &M) const override {
476   }
477 
478   MachineBasicBlock *
479   EmitInstrWithCustomInserter(MachineInstr &MI,
480                               MachineBasicBlock *BB) const override;
481   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
482   void LowerOperationWrapper(SDNode *N, SmallVectorImpl<SDValue> &Results,
483                              SelectionDAG &DAG) const override;
484   void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
485                           SelectionDAG &DAG) const override;
486   const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
487   bool allowTruncateForTailCall(Type *, Type *) const override;
488   bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
489   SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
490                                bool isVarArg,
491                                const SmallVectorImpl<ISD::InputArg> &Ins,
492                                const SDLoc &DL, SelectionDAG &DAG,
493                                SmallVectorImpl<SDValue> &InVals) const override;
494   SDValue LowerCall(CallLoweringInfo &CLI,
495                     SmallVectorImpl<SDValue> &InVals) const override;
496 
497   bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
498                       bool isVarArg,
499                       const SmallVectorImpl<ISD::OutputArg> &Outs,
500                       LLVMContext &Context) const override;
501   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
502                       const SmallVectorImpl<ISD::OutputArg> &Outs,
503                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
504                       SelectionDAG &DAG) const override;
505   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
506 
507   /// Determine which of the bits specified in Mask are known to be either
508   /// zero or one and return them in the KnownZero/KnownOne bitsets.
509   void computeKnownBitsForTargetNode(const SDValue Op,
510                                      KnownBits &Known,
511                                      const APInt &DemandedElts,
512                                      const SelectionDAG &DAG,
513                                      unsigned Depth = 0) const override;
514 
515   /// Determine the number of bits in the operation that are sign bits.
516   unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
517                                            const APInt &DemandedElts,
518                                            const SelectionDAG &DAG,
519                                            unsigned Depth) const override;
520 
getExtendForAtomicOps()521   ISD::NodeType getExtendForAtomicOps() const override {
522     return ISD::ANY_EXTEND;
523   }
524 
supportSwiftError()525   bool supportSwiftError() const override {
526     return true;
527   }
528 
529 private:
530   const SystemZSubtarget &Subtarget;
531 
532   // Implement LowerOperation for individual opcodes.
533   SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode,
534                        const SDLoc &DL, EVT VT,
535                        SDValue CmpOp0, SDValue CmpOp1) const;
536   SDValue lowerVectorSETCC(SelectionDAG &DAG, const SDLoc &DL,
537                            EVT VT, ISD::CondCode CC,
538                            SDValue CmpOp0, SDValue CmpOp1) const;
539   SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
540   SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
541   SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
542   SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
543                              SelectionDAG &DAG) const;
544   SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
545                             SelectionDAG &DAG, unsigned Opcode,
546                             SDValue GOTOffset) const;
547   SDValue lowerThreadPointer(const SDLoc &DL, SelectionDAG &DAG) const;
548   SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
549                                 SelectionDAG &DAG) const;
550   SDValue lowerBlockAddress(BlockAddressSDNode *Node,
551                             SelectionDAG &DAG) const;
552   SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
553   SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
554   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
555   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
556   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
557   SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
558   SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
559   SDValue lowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
560   SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
561   SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
562   SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
563   SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
564   SDValue lowerXALUO(SDValue Op, SelectionDAG &DAG) const;
565   SDValue lowerADDSUBCARRY(SDValue Op, SelectionDAG &DAG) const;
566   SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
567   SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
568   SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
569   SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
570   SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
571   SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
572   SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
573                               unsigned Opcode) const;
574   SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
575   SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
576   SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
577   SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
578   SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
579   SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
580   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
581   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
582   SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
583   SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
584   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
585   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
586   SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
587                                  unsigned UnpackHigh) const;
588   SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
589 
590   bool canTreatAsByteVector(EVT VT) const;
591   SDValue combineExtract(const SDLoc &DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
592                          unsigned Index, DAGCombinerInfo &DCI,
593                          bool Force) const;
594   SDValue combineTruncateExtract(const SDLoc &DL, EVT TruncVT, SDValue Op,
595                                  DAGCombinerInfo &DCI) const;
596   SDValue combineZERO_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
597   SDValue combineSIGN_EXTEND(SDNode *N, DAGCombinerInfo &DCI) const;
598   SDValue combineSIGN_EXTEND_INREG(SDNode *N, DAGCombinerInfo &DCI) const;
599   SDValue combineMERGE(SDNode *N, DAGCombinerInfo &DCI) const;
600   SDValue combineSTORE(SDNode *N, DAGCombinerInfo &DCI) const;
601   SDValue combineEXTRACT_VECTOR_ELT(SDNode *N, DAGCombinerInfo &DCI) const;
602   SDValue combineJOIN_DWORDS(SDNode *N, DAGCombinerInfo &DCI) const;
603   SDValue combineFP_ROUND(SDNode *N, DAGCombinerInfo &DCI) const;
604   SDValue combineBSWAP(SDNode *N, DAGCombinerInfo &DCI) const;
605   SDValue combineBR_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
606   SDValue combineSELECT_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
607   SDValue combineGET_CCMASK(SDNode *N, DAGCombinerInfo &DCI) const;
608 
609   // If the last instruction before MBBI in MBB was some form of COMPARE,
610   // try to replace it with a COMPARE AND BRANCH just before MBBI.
611   // CCMask and Target are the BRC-like operands for the branch.
612   // Return true if the change was made.
613   bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
614                                   MachineBasicBlock::iterator MBBI,
615                                   unsigned CCMask,
616                                   MachineBasicBlock *Target) const;
617 
618   // Implement EmitInstrWithCustomInserter for individual operation types.
619   MachineBasicBlock *emitSelect(MachineInstr &MI, MachineBasicBlock *BB) const;
620   MachineBasicBlock *emitCondStore(MachineInstr &MI, MachineBasicBlock *BB,
621                                    unsigned StoreOpcode, unsigned STOCOpcode,
622                                    bool Invert) const;
623   MachineBasicBlock *emitPair128(MachineInstr &MI,
624                                  MachineBasicBlock *MBB) const;
625   MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
626                                 bool ClearEven) const;
627   MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
628                                           MachineBasicBlock *BB,
629                                           unsigned BinOpcode, unsigned BitSize,
630                                           bool Invert = false) const;
631   MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr &MI,
632                                           MachineBasicBlock *MBB,
633                                           unsigned CompareOpcode,
634                                           unsigned KeepOldMask,
635                                           unsigned BitSize) const;
636   MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr &MI,
637                                         MachineBasicBlock *BB) const;
638   MachineBasicBlock *emitMemMemWrapper(MachineInstr &MI, MachineBasicBlock *BB,
639                                        unsigned Opcode) const;
640   MachineBasicBlock *emitStringWrapper(MachineInstr &MI, MachineBasicBlock *BB,
641                                        unsigned Opcode) const;
642   MachineBasicBlock *emitTransactionBegin(MachineInstr &MI,
643                                           MachineBasicBlock *MBB,
644                                           unsigned Opcode, bool NoFloat) const;
645   MachineBasicBlock *emitLoadAndTestCmp0(MachineInstr &MI,
646                                          MachineBasicBlock *MBB,
647                                          unsigned Opcode) const;
648 
649   const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
650 };
651 } // end namespace llvm
652 
653 #endif
654