1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file includes code for rendering MCInst instances as Intel-style
11 // assembly.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "X86IntelInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/Support/Casting.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <cassert>
26 #include <cstdint>
27
28 using namespace llvm;
29
30 #define DEBUG_TYPE "asm-printer"
31
32 #include "X86GenAsmWriter1.inc"
33
printRegName(raw_ostream & OS,unsigned RegNo) const34 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
35 OS << getRegisterName(RegNo);
36 }
37
printInst(const MCInst * MI,raw_ostream & OS,StringRef Annot,const MCSubtargetInfo & STI)38 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
39 StringRef Annot,
40 const MCSubtargetInfo &STI) {
41 printInstFlags(MI, OS);
42
43 // In 16-bit mode, print data16 as data32.
44 if (MI->getOpcode() == X86::DATA16_PREFIX &&
45 STI.getFeatureBits()[X86::Mode16Bit]) {
46 OS << "\tdata32";
47 } else
48 printInstruction(MI, OS);
49
50 // Next always print the annotation.
51 printAnnotation(OS, Annot);
52
53 // If verbose assembly is enabled, we can print some informative comments.
54 if (CommentStream)
55 EmitAnyX86InstComments(MI, *CommentStream, MII);
56 }
57
printOperand(const MCInst * MI,unsigned OpNo,raw_ostream & O)58 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
59 raw_ostream &O) {
60 const MCOperand &Op = MI->getOperand(OpNo);
61 if (Op.isReg()) {
62 printRegName(O, Op.getReg());
63 } else if (Op.isImm()) {
64 O << formatImm((int64_t)Op.getImm());
65 } else {
66 assert(Op.isExpr() && "unknown operand kind in printOperand");
67 O << "offset ";
68 Op.getExpr()->print(O, &MAI);
69 }
70 }
71
printMemReference(const MCInst * MI,unsigned Op,raw_ostream & O)72 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
73 raw_ostream &O) {
74 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
75 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
76 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
77 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
78
79 // If this has a segment register, print it.
80 printOptionalSegReg(MI, Op + X86::AddrSegmentReg, O);
81
82 O << '[';
83
84 bool NeedPlus = false;
85 if (BaseReg.getReg()) {
86 printOperand(MI, Op+X86::AddrBaseReg, O);
87 NeedPlus = true;
88 }
89
90 if (IndexReg.getReg()) {
91 if (NeedPlus) O << " + ";
92 if (ScaleVal != 1)
93 O << ScaleVal << '*';
94 printOperand(MI, Op+X86::AddrIndexReg, O);
95 NeedPlus = true;
96 }
97
98 if (!DispSpec.isImm()) {
99 if (NeedPlus) O << " + ";
100 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
101 DispSpec.getExpr()->print(O, &MAI);
102 } else {
103 int64_t DispVal = DispSpec.getImm();
104 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
105 if (NeedPlus) {
106 if (DispVal > 0)
107 O << " + ";
108 else {
109 O << " - ";
110 DispVal = -DispVal;
111 }
112 }
113 O << formatImm(DispVal);
114 }
115 }
116
117 O << ']';
118 }
119
printSrcIdx(const MCInst * MI,unsigned Op,raw_ostream & O)120 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
121 raw_ostream &O) {
122 // If this has a segment register, print it.
123 printOptionalSegReg(MI, Op + 1, O);
124 O << '[';
125 printOperand(MI, Op, O);
126 O << ']';
127 }
128
printDstIdx(const MCInst * MI,unsigned Op,raw_ostream & O)129 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
130 raw_ostream &O) {
131 // DI accesses are always ES-based.
132 O << "es:[";
133 printOperand(MI, Op, O);
134 O << ']';
135 }
136
printMemOffset(const MCInst * MI,unsigned Op,raw_ostream & O)137 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
138 raw_ostream &O) {
139 const MCOperand &DispSpec = MI->getOperand(Op);
140
141 // If this has a segment register, print it.
142 printOptionalSegReg(MI, Op + 1, O);
143
144 O << '[';
145
146 if (DispSpec.isImm()) {
147 O << formatImm(DispSpec.getImm());
148 } else {
149 assert(DispSpec.isExpr() && "non-immediate displacement?");
150 DispSpec.getExpr()->print(O, &MAI);
151 }
152
153 O << ']';
154 }
155
printU8Imm(const MCInst * MI,unsigned Op,raw_ostream & O)156 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
157 raw_ostream &O) {
158 if (MI->getOperand(Op).isExpr())
159 return MI->getOperand(Op).getExpr()->print(O, &MAI);
160
161 O << formatImm(MI->getOperand(Op).getImm() & 0xff);
162 }
163