1//===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 MPX instruction set, defining the
11// instructions, and properties of the instructions which are needed for code
12// generation, machine code emission, and analysis.
13//
14//===----------------------------------------------------------------------===//
15
16// FIXME: Investigate a better scheduler class once MPX is used inside LLVM.
17let SchedRW = [WriteSystem] in {
18
19multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
20  def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
21              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
22              Requires<[HasMPX, Not64BitMode]>;
23  def 64rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
24              OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
25              Requires<[HasMPX, In64BitMode]>;
26}
27
28defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
29
30multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
31  def 32rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
32              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
33              Requires<[HasMPX, Not64BitMode]>;
34  def 64rm: I<opc, MRMSrcMem, (outs), (ins  BNDR:$src1, anymem:$src2),
35              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
36              Requires<[HasMPX, In64BitMode]>;
37
38  def 32rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR32:$src2),
39              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
40              Requires<[HasMPX, Not64BitMode]>;
41  def 64rr: I<opc, MRMSrcReg, (outs), (ins  BNDR:$src1, GR64:$src2),
42              OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
43              Requires<[HasMPX, In64BitMode]>;
44}
45defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS, NotMemoryFoldable;
46defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD, NotMemoryFoldable;
47defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD, NotMemoryFoldable;
48
49def BNDMOVrr   : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
50                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
51                  Requires<[HasMPX]>, NotMemoryFoldable;
52let mayLoad = 1 in {
53def BNDMOV32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
54                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
55                  Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
56def BNDMOV64rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
57                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
58                  Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
59}
60let isCodeGenOnly = 1, ForceDisassemble = 1 in
61def BNDMOVrr_REV   : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
62                       "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
63                       Requires<[HasMPX]>, NotMemoryFoldable;
64let mayStore = 1 in {
65def BNDMOV32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
66                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
67                  Requires<[HasMPX, Not64BitMode]>, NotMemoryFoldable;
68def BNDMOV64mr : I<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
69                  "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
70                  Requires<[HasMPX, In64BitMode]>, NotMemoryFoldable;
71
72def BNDSTXmr:      I<0x1B, MRMDestMem, (outs), (ins anymem:$dst, BNDR:$src),
73                    "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
74                    Requires<[HasMPX]>;
75}
76let mayLoad = 1 in
77def BNDLDXrm:      I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins anymem:$src),
78                    "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
79                    Requires<[HasMPX]>;
80} // SchedRW
81