1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6
7  define void @atomicrmw_xchg_i64(i64* %addr) { ret void }
8  define void @atomicrmw_add_i64(i64* %addr) { ret void }
9  define void @atomicrmw_add_i32(i64* %addr) { ret void }
10  define void @atomicrmw_sub_i32(i64* %addr) { ret void }
11  define void @atomicrmw_and_i32(i64* %addr) { ret void }
12  ; nand isn't legal
13  define void @atomicrmw_or_i32(i64* %addr) { ret void }
14  define void @atomicrmw_xor_i32(i64* %addr) { ret void }
15  define void @atomicrmw_min_i32(i64* %addr) { ret void }
16  define void @atomicrmw_max_i32(i64* %addr) { ret void }
17  define void @atomicrmw_umin_i32(i64* %addr) { ret void }
18  define void @atomicrmw_umax_i32(i64* %addr) { ret void }
19...
20
21---
22name:            atomicrmw_xchg_i64
23legalized:       true
24regBankSelected: true
25
26body:             |
27  bb.0:
28    liveins: $x0
29
30    ; CHECK-LABEL: name: atomicrmw_xchg_i64
31    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
32    ; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
33    ; CHECK: [[RES:%[0-9]+]]:gpr64 = SWPX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
34    ; CHECK: $x0 = COPY [[RES]]
35    %0:gpr(p0) = COPY $x0
36    %1:gpr(s64) = G_CONSTANT i64 1
37    %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic 8 on %ir.addr)
38    $x0 = COPY %2(s64)
39...
40---
41name:            atomicrmw_add_i64
42legalized:       true
43regBankSelected: true
44
45body:             |
46  bb.0:
47    liveins: $x0
48
49    ; CHECK-LABEL: name: atomicrmw_add_i64
50    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
51    ; CHECK: [[CST:%[0-9]+]]:gpr64 = MOVi64imm 1
52    ; CHECK: [[RES:%[0-9]+]]:gpr64 = LDADDX [[CST]], [[COPY]] :: (load store monotonic 8 on %ir.addr)
53    ; CHECK: $x0 = COPY [[RES]]
54    %0:gpr(p0) = COPY $x0
55    %1:gpr(s64) = G_CONSTANT i64 1
56    %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic 8 on %ir.addr)
57    $x0 = COPY %2(s64)
58...
59---
60name:            atomicrmw_add_i32
61legalized:       true
62regBankSelected: true
63
64body:             |
65  bb.0:
66    liveins: $x0
67
68    ; CHECK-LABEL: name: atomicrmw_add_i32
69    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
70    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
71    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
72    ; CHECK: $w0 = COPY [[RES]]
73    %0:gpr(p0) = COPY $x0
74    %1:gpr(s32) = G_CONSTANT i32 1
75    %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
76    $w0 = COPY %2(s32)
77...
78
79---
80name:            atomicrmw_sub_i32
81legalized:       true
82regBankSelected: true
83
84body:             |
85  bb.0:
86    liveins: $x0
87
88    ; CHECK-LABEL: name: atomicrmw_sub_i32
89    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
90    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
91    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDADDALW [[CST]], [[COPY]] :: (load store seq_cst 4 on %ir.addr)
92    ; CHECK: $w0 = COPY [[RES]]
93    %0:gpr(p0) = COPY $x0
94    %1:gpr(s32) = G_CONSTANT i32 1
95    %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst 4 on %ir.addr)
96    $w0 = COPY %2(s32)
97...
98
99---
100name:            atomicrmw_and_i32
101legalized:       true
102regBankSelected: true
103
104body:             |
105  bb.0:
106    liveins: $x0
107
108    ; CHECK-LABEL: name: atomicrmw_and_i32
109    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
110    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
111    ; CHECK: [[CST2:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[CST]]
112    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDCLRAW [[CST2]], [[COPY]] :: (load store acquire 4 on %ir.addr)
113    ; CHECK: $w0 = COPY [[RES]]
114    %0:gpr(p0) = COPY $x0
115    %1:gpr(s32) = G_CONSTANT i32 1
116    %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire 4 on %ir.addr)
117    $w0 = COPY %2(s32)
118...
119
120---
121name:            atomicrmw_or_i32
122legalized:       true
123regBankSelected: true
124
125body:             |
126  bb.0:
127    liveins: $x0
128
129    ; CHECK-LABEL: name: atomicrmw_or_i32
130    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
131    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
132    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSETLW [[CST]], [[COPY]] :: (load store release 4 on %ir.addr)
133    ; CHECK: $w0 = COPY [[RES]]
134    %0:gpr(p0) = COPY $x0
135    %1:gpr(s32) = G_CONSTANT i32 1
136    %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release 4 on %ir.addr)
137    $w0 = COPY %2(s32)
138...
139
140---
141name:            atomicrmw_xor_i32
142legalized:       true
143regBankSelected: true
144
145body:             |
146  bb.0:
147    liveins: $x0
148
149    ; CHECK-LABEL: name: atomicrmw_xor_i32
150    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
151    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
152    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDEORALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
153    ; CHECK: $w0 = COPY [[RES]]
154    %0:gpr(p0) = COPY $x0
155    %1:gpr(s32) = G_CONSTANT i32 1
156    %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel 4 on %ir.addr)
157    $w0 = COPY %2(s32)
158...
159
160---
161name:            atomicrmw_min_i32
162legalized:       true
163regBankSelected: true
164
165body:             |
166  bb.0:
167    liveins: $x0
168
169    ; CHECK-LABEL: name: atomicrmw_min_i32
170    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
171    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
172    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
173    ; CHECK: $w0 = COPY [[RES]]
174    %0:gpr(p0) = COPY $x0
175    %1:gpr(s32) = G_CONSTANT i32 1
176    %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
177    $w0 = COPY %2(s32)
178...
179
180---
181name:            atomicrmw_max_i32
182legalized:       true
183regBankSelected: true
184
185body:             |
186  bb.0:
187    liveins: $x0
188
189    ; CHECK-LABEL: name: atomicrmw_max_i32
190    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
191    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
192    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDSMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
193    ; CHECK: $w0 = COPY [[RES]]
194    %0:gpr(p0) = COPY $x0
195    %1:gpr(s32) = G_CONSTANT i32 1
196    %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
197    $w0 = COPY %2(s32)
198...
199
200---
201name:            atomicrmw_umin_i32
202legalized:       true
203regBankSelected: true
204
205body:             |
206  bb.0:
207    liveins: $x0
208
209    ; CHECK-LABEL: name: atomicrmw_umin_i32
210    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
211    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
212    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMINALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
213    ; CHECK: $w0 = COPY [[RES]]
214    %0:gpr(p0) = COPY $x0
215    %1:gpr(s32) = G_CONSTANT i32 1
216    %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel 4 on %ir.addr)
217    $w0 = COPY %2(s32)
218...
219
220---
221name:            atomicrmw_umax_i32
222legalized:       true
223regBankSelected: true
224
225body:             |
226  bb.0:
227    liveins: $x0
228
229    ; CHECK-LABEL: name: atomicrmw_umax_i32
230    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
231    ; CHECK: [[CST:%[0-9]+]]:gpr32 = MOVi32imm 1
232    ; CHECK: [[RES:%[0-9]+]]:gpr32 = LDUMAXALW [[CST]], [[COPY]] :: (load store acq_rel 4 on %ir.addr)
233    ; CHECK: $w0 = COPY [[RES]]
234    %0:gpr(p0) = COPY $x0
235    %1:gpr(s32) = G_CONSTANT i32 1
236    %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel 4 on %ir.addr)
237    $w0 = COPY %2(s32)
238...
239