1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 7 define void @add_s32_gpr() { ret void } 8 define void @add_s64_gpr() { ret void } 9 10 define void @add_imm_s32_gpr() { ret void } 11 define void @add_imm_s64_gpr() { ret void } 12 13 define void @add_imm_s32_gpr_bb() { ret void } 14 15 define void @sub_s32_gpr() { ret void } 16 define void @sub_s64_gpr() { ret void } 17 18 define void @or_s32_gpr() { ret void } 19 define void @or_s64_gpr() { ret void } 20 define void @or_v2s32_fpr() { ret void } 21 22 define void @and_s32_gpr() { ret void } 23 define void @and_s64_gpr() { ret void } 24 25 define void @shl_s32_gpr() { ret void } 26 define void @shl_s64_gpr() { ret void } 27 28 define void @lshr_s32_gpr() { ret void } 29 define void @lshr_s64_gpr() { ret void } 30 31 define void @ashr_s32_gpr() { ret void } 32 define void @ashr_s64_gpr() { ret void } 33 34 define void @mul_s32_gpr() { ret void } 35 define void @mul_s64_gpr() { ret void } 36 37 define void @mulh_s64_gpr() { ret void } 38 39 define void @sdiv_s32_gpr() { ret void } 40 define void @sdiv_s64_gpr() { ret void } 41 42 define void @udiv_s32_gpr() { ret void } 43 define void @udiv_s64_gpr() { ret void } 44 45 define void @fadd_s32_fpr() { ret void } 46 define void @fadd_s64_fpr() { ret void } 47 48 define void @fsub_s32_fpr() { ret void } 49 define void @fsub_s64_fpr() { ret void } 50 51 define void @fmul_s32_fpr() { ret void } 52 define void @fmul_s64_fpr() { ret void } 53 54 define void @fdiv_s32_fpr() { ret void } 55 define void @fdiv_s64_fpr() { ret void } 56 57... 58 59--- 60# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. 61# Also check that we constrain the register class of the COPY to GPR32. 62name: add_s32_gpr 63legalized: true 64regBankSelected: true 65 66registers: 67 - { id: 0, class: gpr } 68 - { id: 1, class: gpr } 69 - { id: 2, class: gpr } 70 71body: | 72 bb.0: 73 liveins: $w0, $w1 74 75 ; CHECK-LABEL: name: add_s32_gpr 76 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 77 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 78 ; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] 79 ; CHECK: $w0 = COPY [[ADDWrr]] 80 %0(s32) = COPY $w0 81 %1(s32) = COPY $w1 82 %2(s32) = G_ADD %0, %1 83 $w0 = COPY %2(s32) 84... 85 86--- 87# Same as add_s32_gpr, for 64-bit operations. 88name: add_s64_gpr 89legalized: true 90regBankSelected: true 91 92registers: 93 - { id: 0, class: gpr } 94 - { id: 1, class: gpr } 95 - { id: 2, class: gpr } 96 97body: | 98 bb.0: 99 liveins: $x0, $x1 100 101 ; CHECK-LABEL: name: add_s64_gpr 102 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 103 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 104 ; CHECK: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] 105 ; CHECK: $x0 = COPY [[ADDXrr]] 106 %0(s64) = COPY $x0 107 %1(s64) = COPY $x1 108 %2(s64) = G_ADD %0, %1 109 $x0 = COPY %2(s64) 110... 111 112--- 113name: add_imm_s32_gpr 114legalized: true 115regBankSelected: true 116 117registers: 118 - { id: 0, class: gpr } 119 - { id: 1, class: gpr } 120 - { id: 2, class: gpr } 121 122body: | 123 bb.0: 124 liveins: $w0, $w1 125 126 ; CHECK-LABEL: name: add_imm_s32_gpr 127 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 128 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 129 ; CHECK: $w0 = COPY [[ADDWri]] 130 %0(s32) = COPY $w0 131 %1(s32) = G_CONSTANT i32 1 132 %2(s32) = G_ADD %0, %1 133 $w0 = COPY %2(s32) 134... 135 136--- 137name: add_imm_s64_gpr 138legalized: true 139regBankSelected: true 140 141registers: 142 - { id: 0, class: gpr } 143 - { id: 1, class: gpr } 144 - { id: 2, class: gpr } 145 146body: | 147 bb.0: 148 liveins: $x0, $w1 149 150 ; CHECK-LABEL: name: add_imm_s64_gpr 151 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 152 ; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0 153 ; CHECK: $x0 = COPY [[ADDXri]] 154 %0(s64) = COPY $x0 155 %1(s64) = G_CONSTANT i32 1 156 %2(s64) = G_ADD %0, %1 157 $x0 = COPY %2(s64) 158... 159 160--- 161name: add_imm_s32_gpr_bb 162legalized: true 163regBankSelected: true 164 165registers: 166 - { id: 0, class: gpr } 167 - { id: 1, class: gpr } 168 - { id: 2, class: gpr } 169 170body: | 171 ; CHECK-LABEL: name: add_imm_s32_gpr_bb 172 ; CHECK: bb.0: 173 ; CHECK: successors: %bb.1(0x80000000) 174 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 175 ; CHECK: B %bb.1 176 ; CHECK: bb.1: 177 ; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 178 ; CHECK: $w0 = COPY [[ADDWri]] 179 bb.0: 180 liveins: $w0, $w1 181 successors: %bb.1 182 183 %0(s32) = COPY $w0 184 %1(s32) = G_CONSTANT i32 1 185 G_BR %bb.1 186 187 bb.1: 188 %2(s32) = G_ADD %0, %1 189 $w0 = COPY %2(s32) 190... 191 192--- 193# Same as add_s32_gpr, for G_SUB operations. 194name: sub_s32_gpr 195legalized: true 196regBankSelected: true 197 198registers: 199 - { id: 0, class: gpr } 200 - { id: 1, class: gpr } 201 - { id: 2, class: gpr } 202 203body: | 204 bb.0: 205 liveins: $w0, $w1 206 207 ; CHECK-LABEL: name: sub_s32_gpr 208 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 209 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 210 ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv 211 ; CHECK: $w0 = COPY [[SUBSWrr]] 212 %0(s32) = COPY $w0 213 %1(s32) = COPY $w1 214 %2(s32) = G_SUB %0, %1 215 $w0 = COPY %2(s32) 216... 217 218--- 219# Same as add_s64_gpr, for G_SUB operations. 220name: sub_s64_gpr 221legalized: true 222regBankSelected: true 223 224registers: 225 - { id: 0, class: gpr } 226 - { id: 1, class: gpr } 227 - { id: 2, class: gpr } 228 229body: | 230 bb.0: 231 liveins: $x0, $x1 232 233 ; CHECK-LABEL: name: sub_s64_gpr 234 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 235 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 236 ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv 237 ; CHECK: $x0 = COPY [[SUBSXrr]] 238 %0(s64) = COPY $x0 239 %1(s64) = COPY $x1 240 %2(s64) = G_SUB %0, %1 241 $x0 = COPY %2(s64) 242... 243 244--- 245# Same as add_s32_gpr, for G_OR operations. 246name: or_s32_gpr 247legalized: true 248regBankSelected: true 249 250registers: 251 - { id: 0, class: gpr } 252 - { id: 1, class: gpr } 253 - { id: 2, class: gpr } 254 255body: | 256 bb.0: 257 liveins: $w0, $w1 258 259 ; CHECK-LABEL: name: or_s32_gpr 260 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 261 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 262 ; CHECK: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]] 263 ; CHECK: $w0 = COPY [[ORRWrr]] 264 %0(s32) = COPY $w0 265 %1(s32) = COPY $w1 266 %2(s32) = G_OR %0, %1 267 $w0 = COPY %2(s32) 268... 269 270--- 271# Same as add_s64_gpr, for G_OR operations. 272name: or_s64_gpr 273legalized: true 274regBankSelected: true 275 276registers: 277 - { id: 0, class: gpr } 278 - { id: 1, class: gpr } 279 - { id: 2, class: gpr } 280 281body: | 282 bb.0: 283 liveins: $x0, $x1 284 285 ; CHECK-LABEL: name: or_s64_gpr 286 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 287 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 288 ; CHECK: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]] 289 ; CHECK: $x0 = COPY [[ORRXrr]] 290 %0(s64) = COPY $x0 291 %1(s64) = COPY $x1 292 %2(s64) = G_OR %0, %1 293 $x0 = COPY %2(s64) 294... 295 296--- 297# 64-bit G_OR on vector registers. 298name: or_v2s32_fpr 299legalized: true 300regBankSelected: true 301# 302registers: 303 - { id: 0, class: fpr } 304 - { id: 1, class: fpr } 305 - { id: 2, class: fpr } 306 307# The actual OR does not matter as long as it is operating 308# on 64-bit width vector. 309body: | 310 bb.0: 311 liveins: $d0, $d1 312 313 ; CHECK-LABEL: name: or_v2s32_fpr 314 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 315 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 316 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] 317 ; CHECK: $d0 = COPY [[ORRv8i8_]] 318 %0(<2 x s32>) = COPY $d0 319 %1(<2 x s32>) = COPY $d1 320 %2(<2 x s32>) = G_OR %0, %1 321 $d0 = COPY %2(<2 x s32>) 322... 323 324--- 325# Same as add_s32_gpr, for G_AND operations. 326name: and_s32_gpr 327legalized: true 328regBankSelected: true 329 330registers: 331 - { id: 0, class: gpr } 332 - { id: 1, class: gpr } 333 - { id: 2, class: gpr } 334 335body: | 336 bb.0: 337 liveins: $w0, $w1 338 339 ; CHECK-LABEL: name: and_s32_gpr 340 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 341 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 342 ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]] 343 ; CHECK: $w0 = COPY [[ANDWrr]] 344 %0(s32) = COPY $w0 345 %1(s32) = COPY $w1 346 %2(s32) = G_AND %0, %1 347 $w0 = COPY %2(s32) 348... 349 350--- 351# Same as add_s64_gpr, for G_AND operations. 352name: and_s64_gpr 353legalized: true 354regBankSelected: true 355 356registers: 357 - { id: 0, class: gpr } 358 - { id: 1, class: gpr } 359 - { id: 2, class: gpr } 360 361body: | 362 bb.0: 363 liveins: $x0, $x1 364 365 ; CHECK-LABEL: name: and_s64_gpr 366 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 367 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 368 ; CHECK: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]] 369 ; CHECK: $x0 = COPY [[ANDXrr]] 370 %0(s64) = COPY $x0 371 %1(s64) = COPY $x1 372 %2(s64) = G_AND %0, %1 373 $x0 = COPY %2(s64) 374... 375 376--- 377# Same as add_s32_gpr, for G_SHL operations. 378name: shl_s32_gpr 379legalized: true 380regBankSelected: true 381 382registers: 383 - { id: 0, class: gpr } 384 - { id: 1, class: gpr } 385 - { id: 2, class: gpr } 386 387body: | 388 bb.0: 389 liveins: $w0, $w1 390 391 ; CHECK-LABEL: name: shl_s32_gpr 392 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 393 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 394 ; CHECK: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]] 395 ; CHECK: $w0 = COPY [[LSLVWr]] 396 %0(s32) = COPY $w0 397 %1(s32) = COPY $w1 398 %2(s32) = G_SHL %0, %1 399 $w0 = COPY %2(s32) 400... 401 402--- 403# Same as add_s64_gpr, for G_SHL operations. 404name: shl_s64_gpr 405legalized: true 406regBankSelected: true 407 408registers: 409 - { id: 0, class: gpr } 410 - { id: 1, class: gpr } 411 - { id: 2, class: gpr } 412 413body: | 414 bb.0: 415 liveins: $x0, $x1 416 417 ; CHECK-LABEL: name: shl_s64_gpr 418 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 419 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 420 ; CHECK: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]] 421 ; CHECK: $x0 = COPY [[LSLVXr]] 422 %0(s64) = COPY $x0 423 %1(s64) = COPY $x1 424 %2(s64) = G_SHL %0, %1 425 $x0 = COPY %2(s64) 426... 427 428--- 429# Same as add_s32_gpr, for G_LSHR operations. 430name: lshr_s32_gpr 431legalized: true 432regBankSelected: true 433 434registers: 435 - { id: 0, class: gpr } 436 - { id: 1, class: gpr } 437 - { id: 2, class: gpr } 438 439body: | 440 bb.0: 441 liveins: $w0, $w1 442 443 ; CHECK-LABEL: name: lshr_s32_gpr 444 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 445 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 446 ; CHECK: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] 447 ; CHECK: $w0 = COPY [[LSRVWr]] 448 %0(s32) = COPY $w0 449 %1(s32) = COPY $w1 450 %2(s32) = G_LSHR %0, %1 451 $w0 = COPY %2(s32) 452... 453 454--- 455# Same as add_s64_gpr, for G_LSHR operations. 456name: lshr_s64_gpr 457legalized: true 458regBankSelected: true 459 460registers: 461 - { id: 0, class: gpr } 462 - { id: 1, class: gpr } 463 - { id: 2, class: gpr } 464 465body: | 466 bb.0: 467 liveins: $x0, $x1 468 469 ; CHECK-LABEL: name: lshr_s64_gpr 470 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 471 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 472 ; CHECK: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]] 473 ; CHECK: $x0 = COPY [[LSRVXr]] 474 %0(s64) = COPY $x0 475 %1(s64) = COPY $x1 476 %2(s64) = G_LSHR %0, %1 477 $x0 = COPY %2(s64) 478... 479 480--- 481# Same as add_s32_gpr, for G_ASHR operations. 482name: ashr_s32_gpr 483legalized: true 484regBankSelected: true 485 486registers: 487 - { id: 0, class: gpr } 488 - { id: 1, class: gpr } 489 - { id: 2, class: gpr } 490 491body: | 492 bb.0: 493 liveins: $w0, $w1 494 495 ; CHECK-LABEL: name: ashr_s32_gpr 496 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 497 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 498 ; CHECK: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] 499 ; CHECK: $w0 = COPY [[ASRVWr]] 500 %0(s32) = COPY $w0 501 %1(s32) = COPY $w1 502 %2(s32) = G_ASHR %0, %1 503 $w0 = COPY %2(s32) 504... 505 506--- 507# Same as add_s64_gpr, for G_ASHR operations. 508name: ashr_s64_gpr 509legalized: true 510regBankSelected: true 511 512registers: 513 - { id: 0, class: gpr } 514 - { id: 1, class: gpr } 515 - { id: 2, class: gpr } 516 517body: | 518 bb.0: 519 liveins: $x0, $x1 520 521 ; CHECK-LABEL: name: ashr_s64_gpr 522 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 523 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 524 ; CHECK: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]] 525 ; CHECK: $x0 = COPY [[ASRVXr]] 526 %0(s64) = COPY $x0 527 %1(s64) = COPY $x1 528 %2(s64) = G_ASHR %0, %1 529 $x0 = COPY %2(s64) 530... 531 532--- 533# Check that we select s32 GPR G_MUL. This is trickier than other binops because 534# there is only MADDWrrr, and we have to use the WZR physreg. 535name: mul_s32_gpr 536legalized: true 537regBankSelected: true 538 539registers: 540 - { id: 0, class: gpr } 541 - { id: 1, class: gpr } 542 - { id: 2, class: gpr } 543 544body: | 545 bb.0: 546 liveins: $w0, $w1 547 548 ; CHECK-LABEL: name: mul_s32_gpr 549 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 550 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 551 ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr 552 ; CHECK: $w0 = COPY [[MADDWrrr]] 553 %0(s32) = COPY $w0 554 %1(s32) = COPY $w1 555 %2(s32) = G_MUL %0, %1 556 $w0 = COPY %2(s32) 557... 558 559--- 560# Same as mul_s32_gpr for the s64 type. 561name: mul_s64_gpr 562legalized: true 563regBankSelected: true 564 565registers: 566 - { id: 0, class: gpr } 567 - { id: 1, class: gpr } 568 - { id: 2, class: gpr } 569 570body: | 571 bb.0: 572 liveins: $x0, $x1 573 574 ; CHECK-LABEL: name: mul_s64_gpr 575 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 576 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 577 ; CHECK: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr 578 ; CHECK: $x0 = COPY [[MADDXrrr]] 579 %0(s64) = COPY $x0 580 %1(s64) = COPY $x1 581 %2(s64) = G_MUL %0, %1 582 $x0 = COPY %2(s64) 583... 584 585--- 586# Same as mul_s32_gpr for the s64 type. 587name: mulh_s64_gpr 588legalized: true 589regBankSelected: true 590 591 592body: | 593 bb.0: 594 liveins: $x0, $x1 595 596 ; CHECK-LABEL: name: mulh_s64_gpr 597 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 598 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 599 ; CHECK: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]] 600 ; CHECK: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]] 601 ; CHECK: $x0 = COPY [[SMULHrr]] 602 ; CHECK: $x0 = COPY [[UMULHrr]] 603 %0:gpr(s64) = COPY $x0 604 %1:gpr(s64) = COPY $x1 605 %2:gpr(s64) = G_SMULH %0, %1 606 %3:gpr(s64) = G_UMULH %0, %1 607 $x0 = COPY %2(s64) 608 $x0 = COPY %3(s64) 609... 610 611--- 612# Same as add_s32_gpr, for G_SDIV operations. 613name: sdiv_s32_gpr 614legalized: true 615regBankSelected: true 616 617registers: 618 - { id: 0, class: gpr } 619 - { id: 1, class: gpr } 620 - { id: 2, class: gpr } 621 622body: | 623 bb.0: 624 liveins: $w0, $w1 625 626 ; CHECK-LABEL: name: sdiv_s32_gpr 627 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 628 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 629 ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]] 630 ; CHECK: $w0 = COPY [[SDIVWr]] 631 %0(s32) = COPY $w0 632 %1(s32) = COPY $w1 633 %2(s32) = G_SDIV %0, %1 634 $w0 = COPY %2(s32) 635... 636 637--- 638# Same as add_s64_gpr, for G_SDIV operations. 639name: sdiv_s64_gpr 640legalized: true 641regBankSelected: true 642 643registers: 644 - { id: 0, class: gpr } 645 - { id: 1, class: gpr } 646 - { id: 2, class: gpr } 647 648body: | 649 bb.0: 650 liveins: $x0, $x1 651 652 ; CHECK-LABEL: name: sdiv_s64_gpr 653 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 654 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 655 ; CHECK: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]] 656 ; CHECK: $x0 = COPY [[SDIVXr]] 657 %0(s64) = COPY $x0 658 %1(s64) = COPY $x1 659 %2(s64) = G_SDIV %0, %1 660 $x0 = COPY %2(s64) 661... 662 663--- 664# Same as add_s32_gpr, for G_UDIV operations. 665name: udiv_s32_gpr 666legalized: true 667regBankSelected: true 668 669registers: 670 - { id: 0, class: gpr } 671 - { id: 1, class: gpr } 672 - { id: 2, class: gpr } 673 674body: | 675 bb.0: 676 liveins: $w0, $w1 677 678 ; CHECK-LABEL: name: udiv_s32_gpr 679 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 680 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 681 ; CHECK: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]] 682 ; CHECK: $w0 = COPY [[UDIVWr]] 683 %0(s32) = COPY $w0 684 %1(s32) = COPY $w1 685 %2(s32) = G_UDIV %0, %1 686 $w0 = COPY %2(s32) 687... 688 689--- 690# Same as add_s64_gpr, for G_UDIV operations. 691name: udiv_s64_gpr 692legalized: true 693regBankSelected: true 694 695registers: 696 - { id: 0, class: gpr } 697 - { id: 1, class: gpr } 698 - { id: 2, class: gpr } 699 700body: | 701 bb.0: 702 liveins: $x0, $x1 703 704 ; CHECK-LABEL: name: udiv_s64_gpr 705 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 706 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 707 ; CHECK: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]] 708 ; CHECK: $x0 = COPY [[UDIVXr]] 709 %0(s64) = COPY $x0 710 %1(s64) = COPY $x1 711 %2(s64) = G_UDIV %0, %1 712 $x0 = COPY %2(s64) 713... 714 715--- 716# Check that we select a s32 FPR G_FADD into FADDSrr. 717name: fadd_s32_fpr 718legalized: true 719regBankSelected: true 720 721registers: 722 - { id: 0, class: fpr } 723 - { id: 1, class: fpr } 724 - { id: 2, class: fpr } 725 726body: | 727 bb.0: 728 liveins: $s0, $s1 729 730 ; CHECK-LABEL: name: fadd_s32_fpr 731 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 732 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 733 ; CHECK: [[FADDSrr:%[0-9]+]]:fpr32 = FADDSrr [[COPY]], [[COPY1]] 734 ; CHECK: $s0 = COPY [[FADDSrr]] 735 %0(s32) = COPY $s0 736 %1(s32) = COPY $s1 737 %2(s32) = G_FADD %0, %1 738 $s0 = COPY %2(s32) 739... 740 741--- 742name: fadd_s64_fpr 743legalized: true 744regBankSelected: true 745 746registers: 747 - { id: 0, class: fpr } 748 - { id: 1, class: fpr } 749 - { id: 2, class: fpr } 750 751body: | 752 bb.0: 753 liveins: $d0, $d1 754 755 ; CHECK-LABEL: name: fadd_s64_fpr 756 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 757 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 758 ; CHECK: [[FADDDrr:%[0-9]+]]:fpr64 = FADDDrr [[COPY]], [[COPY1]] 759 ; CHECK: $d0 = COPY [[FADDDrr]] 760 %0(s64) = COPY $d0 761 %1(s64) = COPY $d1 762 %2(s64) = G_FADD %0, %1 763 $d0 = COPY %2(s64) 764... 765 766--- 767name: fsub_s32_fpr 768legalized: true 769regBankSelected: true 770 771registers: 772 - { id: 0, class: fpr } 773 - { id: 1, class: fpr } 774 - { id: 2, class: fpr } 775 776body: | 777 bb.0: 778 liveins: $s0, $s1 779 780 ; CHECK-LABEL: name: fsub_s32_fpr 781 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 782 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 783 ; CHECK: [[FSUBSrr:%[0-9]+]]:fpr32 = FSUBSrr [[COPY]], [[COPY1]] 784 ; CHECK: $s0 = COPY [[FSUBSrr]] 785 %0(s32) = COPY $s0 786 %1(s32) = COPY $s1 787 %2(s32) = G_FSUB %0, %1 788 $s0 = COPY %2(s32) 789... 790 791--- 792name: fsub_s64_fpr 793legalized: true 794regBankSelected: true 795 796registers: 797 - { id: 0, class: fpr } 798 - { id: 1, class: fpr } 799 - { id: 2, class: fpr } 800 801body: | 802 bb.0: 803 liveins: $d0, $d1 804 805 ; CHECK-LABEL: name: fsub_s64_fpr 806 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 807 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 808 ; CHECK: [[FSUBDrr:%[0-9]+]]:fpr64 = FSUBDrr [[COPY]], [[COPY1]] 809 ; CHECK: $d0 = COPY [[FSUBDrr]] 810 %0(s64) = COPY $d0 811 %1(s64) = COPY $d1 812 %2(s64) = G_FSUB %0, %1 813 $d0 = COPY %2(s64) 814... 815 816--- 817name: fmul_s32_fpr 818legalized: true 819regBankSelected: true 820 821registers: 822 - { id: 0, class: fpr } 823 - { id: 1, class: fpr } 824 - { id: 2, class: fpr } 825 826body: | 827 bb.0: 828 liveins: $s0, $s1 829 830 ; CHECK-LABEL: name: fmul_s32_fpr 831 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 832 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 833 ; CHECK: [[FMULSrr:%[0-9]+]]:fpr32 = FMULSrr [[COPY]], [[COPY1]] 834 ; CHECK: $s0 = COPY [[FMULSrr]] 835 %0(s32) = COPY $s0 836 %1(s32) = COPY $s1 837 %2(s32) = G_FMUL %0, %1 838 $s0 = COPY %2(s32) 839... 840 841--- 842name: fmul_s64_fpr 843legalized: true 844regBankSelected: true 845 846registers: 847 - { id: 0, class: fpr } 848 - { id: 1, class: fpr } 849 - { id: 2, class: fpr } 850 851body: | 852 bb.0: 853 liveins: $d0, $d1 854 855 ; CHECK-LABEL: name: fmul_s64_fpr 856 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 857 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 858 ; CHECK: [[FMULDrr:%[0-9]+]]:fpr64 = FMULDrr [[COPY]], [[COPY1]] 859 ; CHECK: $d0 = COPY [[FMULDrr]] 860 %0(s64) = COPY $d0 861 %1(s64) = COPY $d1 862 %2(s64) = G_FMUL %0, %1 863 $d0 = COPY %2(s64) 864... 865 866--- 867name: fdiv_s32_fpr 868legalized: true 869regBankSelected: true 870 871registers: 872 - { id: 0, class: fpr } 873 - { id: 1, class: fpr } 874 - { id: 2, class: fpr } 875 876body: | 877 bb.0: 878 liveins: $s0, $s1 879 880 ; CHECK-LABEL: name: fdiv_s32_fpr 881 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 882 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 883 ; CHECK: [[FDIVSrr:%[0-9]+]]:fpr32 = FDIVSrr [[COPY]], [[COPY1]] 884 ; CHECK: $s0 = COPY [[FDIVSrr]] 885 %0(s32) = COPY $s0 886 %1(s32) = COPY $s1 887 %2(s32) = G_FDIV %0, %1 888 $s0 = COPY %2(s32) 889... 890 891--- 892name: fdiv_s64_fpr 893legalized: true 894regBankSelected: true 895 896registers: 897 - { id: 0, class: fpr } 898 - { id: 1, class: fpr } 899 - { id: 2, class: fpr } 900 901body: | 902 bb.0: 903 liveins: $d0, $d1 904 905 ; CHECK-LABEL: name: fdiv_s64_fpr 906 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 907 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 908 ; CHECK: [[FDIVDrr:%[0-9]+]]:fpr64 = FDIVDrr [[COPY]], [[COPY1]] 909 ; CHECK: $d0 = COPY [[FDIVDrr]] 910 %0(s64) = COPY $d0 911 %1(s64) = COPY $d1 912 %2(s64) = G_FDIV %0, %1 913 $d0 = COPY %2(s64) 914... 915