1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6
7  define void @sdiv_s32_gpr() { ret void }
8...
9
10---
11# Check that we select a 32-bit GPR sdiv intrinsic into SDIVWrr for GPR32.
12# Also check that we constrain the register class of the COPY to GPR32.
13name:            sdiv_s32_gpr
14legalized:       true
15regBankSelected: true
16
17registers:
18  - { id: 0, class: gpr }
19  - { id: 1, class: gpr }
20  - { id: 2, class: gpr }
21
22body:             |
23  bb.0:
24    liveins: $w0, $w1
25
26    ; CHECK-LABEL: name: sdiv_s32_gpr
27    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
28    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
29    ; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]]
30    ; CHECK: $w0 = COPY [[SDIVWr]]
31    %0(s32) = COPY $w0
32    %1(s32) = COPY $w1
33    %2(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.sdiv.i32), %0, %1
34    $w0 = COPY %2(s32)
35...
36