1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \ 3# RUN: -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \ 4# RUN: -o - | FileCheck %s 5--- 6name: test_rule14_id188_at_idx1067 7alignment: 2 8legalized: true 9regBankSelected: true 10tracksRegLiveness: true 11registers: 12 - { id: 0, class: fpr } 13 - { id: 1, class: fpr } 14liveins: 15 - { reg: '$d0', virtual-reg: '%1' } 16body: | 17 bb.0.entry: 18 liveins: $d0 19 20 ; CHECK-LABEL: name: test_rule14_id188_at_idx1067 21 ; CHECK: liveins: $d0 22 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 23 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 24 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) 25 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 26 %1:fpr(p0) = COPY $d0 27 %0:fpr(s128) = G_LOAD %1(p0) :: (load 16) 28 $noreg = PATCHABLE_RET %0(s128) 29 30... 31--- 32name: test_rule21_id2237_at_idx1449 33alignment: 2 34legalized: true 35regBankSelected: true 36tracksRegLiveness: true 37registers: 38 - { id: 0, class: fpr } 39 - { id: 1, class: fpr } 40liveins: 41 - { reg: '$d0', virtual-reg: '%0' } 42 - { reg: '$d1', virtual-reg: '%1' } 43body: | 44 bb.0.entry: 45 liveins: $d0, $d1 46 47 ; CHECK-LABEL: name: test_rule21_id2237_at_idx1449 48 ; CHECK: liveins: $d0, $d1 49 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 50 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 51 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 52 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) 53 ; CHECK: $noreg = PATCHABLE_RET 54 %1:fpr(p0) = COPY $d1 55 %0:fpr(<8 x s8>) = COPY $d0 56 G_STORE %0(<8 x s8>), %1(p0) :: (store 8) 57 $noreg = PATCHABLE_RET 58 59... 60--- 61name: test_rule22_id2238_at_idx1505 62alignment: 2 63legalized: true 64regBankSelected: true 65tracksRegLiveness: true 66registers: 67 - { id: 0, class: fpr } 68 - { id: 1, class: fpr } 69liveins: 70 - { reg: '$d0', virtual-reg: '%0' } 71 - { reg: '$d1', virtual-reg: '%1' } 72body: | 73 bb.0.entry: 74 liveins: $d0, $d1 75 76 ; CHECK-LABEL: name: test_rule22_id2238_at_idx1505 77 ; CHECK: liveins: $d0, $d1 78 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 79 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 80 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 81 ; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store 8) 82 ; CHECK: $noreg = PATCHABLE_RET 83 %1:fpr(p0) = COPY $d1 84 %0:fpr(<4 x s16>) = COPY $d0 85 G_STORE %0(<4 x s16>), %1(p0) :: (store 8) 86 $noreg = PATCHABLE_RET 87 88... 89--- 90name: test_rule27_id2243_at_idx1781 91alignment: 2 92legalized: true 93regBankSelected: true 94tracksRegLiveness: true 95registers: 96 - { id: 0, class: fpr } 97 - { id: 1, class: fpr } 98liveins: 99 - { reg: '$q0', virtual-reg: '%0' } 100 - { reg: '$d0', virtual-reg: '%1' } 101body: | 102 bb.0.entry: 103 liveins: $q0, $d0 104 105 ; CHECK-LABEL: name: test_rule27_id2243_at_idx1781 106 ; CHECK: liveins: $q0, $d0 107 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 108 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 109 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 110 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) 111 ; CHECK: $noreg = PATCHABLE_RET 112 %1:fpr(p0) = COPY $d0 113 %0:fpr(<4 x s32>) = COPY $q0 114 G_STORE %0(<4 x s32>), %1(p0) :: (store 16) 115 $noreg = PATCHABLE_RET 116 117... 118--- 119name: test_rule28_id2244_at_idx1837 120alignment: 2 121legalized: true 122regBankSelected: true 123tracksRegLiveness: true 124registers: 125 - { id: 0, class: fpr } 126 - { id: 1, class: fpr } 127liveins: 128 - { reg: '$q0', virtual-reg: '%0' } 129 - { reg: '$d0', virtual-reg: '%1' } 130body: | 131 bb.0.entry: 132 liveins: $q0, $d0 133 134 ; CHECK-LABEL: name: test_rule28_id2244_at_idx1837 135 ; CHECK: liveins: $q0, $d0 136 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 137 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 138 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 139 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) 140 ; CHECK: $noreg = PATCHABLE_RET 141 %1:fpr(p0) = COPY $d0 142 %0:fpr(<2 x s64>) = COPY $q0 143 G_STORE %0(<2 x s64>), %1(p0) :: (store 16) 144 $noreg = PATCHABLE_RET 145 146... 147--- 148name: test_rule29_id2245_at_idx1893 149alignment: 2 150legalized: true 151regBankSelected: true 152tracksRegLiveness: true 153registers: 154 - { id: 0, class: fpr } 155 - { id: 1, class: fpr } 156liveins: 157 - { reg: '$q0', virtual-reg: '%0' } 158 - { reg: '$d0', virtual-reg: '%1' } 159body: | 160 bb.0.entry: 161 liveins: $q0, $d0 162 163 ; CHECK-LABEL: name: test_rule29_id2245_at_idx1893 164 ; CHECK: liveins: $q0, $d0 165 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 166 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 167 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 168 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) 169 ; CHECK: $noreg = PATCHABLE_RET 170 %1:fpr(p0) = COPY $d0 171 %0:fpr(<16 x s8>) = COPY $q0 172 G_STORE %0(<16 x s8>), %1(p0) :: (store 16) 173 $noreg = PATCHABLE_RET 174 175... 176--- 177name: test_rule30_id2246_at_idx1949 178alignment: 2 179legalized: true 180regBankSelected: true 181tracksRegLiveness: true 182registers: 183 - { id: 0, class: fpr } 184 - { id: 1, class: fpr } 185liveins: 186 - { reg: '$q0', virtual-reg: '%0' } 187 - { reg: '$d0', virtual-reg: '%1' } 188body: | 189 bb.0.entry: 190 liveins: $q0, $d0 191 192 ; CHECK-LABEL: name: test_rule30_id2246_at_idx1949 193 ; CHECK: liveins: $q0, $d0 194 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 195 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 196 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 197 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) 198 ; CHECK: $noreg = PATCHABLE_RET 199 %1:fpr(p0) = COPY $d0 200 %0:fpr(<8 x s16>) = COPY $q0 201 G_STORE %0(<8 x s16>), %1(p0) :: (store 16) 202 $noreg = PATCHABLE_RET 203 204... 205--- 206name: test_rule34_id2250_at_idx2173 207alignment: 2 208legalized: true 209regBankSelected: true 210tracksRegLiveness: true 211registers: 212 - { id: 0, class: fpr } 213 - { id: 1, class: fpr } 214liveins: 215 - { reg: '$q0', virtual-reg: '%0' } 216 - { reg: '$d0', virtual-reg: '%1' } 217body: | 218 bb.0.entry: 219 liveins: $q0, $d0 220 221 ; CHECK-LABEL: name: test_rule34_id2250_at_idx2173 222 ; CHECK: liveins: $q0, $d0 223 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 224 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 225 ; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]] 226 ; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store 16) 227 ; CHECK: $noreg = PATCHABLE_RET 228 %1:fpr(p0) = COPY $d0 229 %0:fpr(s128) = COPY $q0 230 G_STORE %0(s128), %1(p0) :: (store 16) 231 $noreg = PATCHABLE_RET 232 233... 234# The rules that generated this test has changed. The generator should be rerun 235--- 236name: test_rule92_id2150_at_idx7770 237alignment: 2 238legalized: true 239regBankSelected: true 240tracksRegLiveness: true 241registers: 242 - { id: 0, class: gpr } 243 - { id: 1, class: gpr } 244 - { id: 2, class: gpr } 245liveins: 246 - { reg: '$x0', virtual-reg: '%2' } 247body: | 248 bb.0.entry: 249 liveins: $x0 250 251 ; CHECK-LABEL: name: test_rule92_id2150_at_idx7770 252 ; CHECK: liveins: $x0 253 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 254 ; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1) 255 ; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]] 256 %2:gpr(p0) = COPY $x0 257 %0:gpr(s32) = G_LOAD %2(p0) :: (load 1) 258 $noreg = PATCHABLE_RET %0(s32) 259 260... 261# The rules that generated this test has changed. The generator should be rerun 262--- 263name: test_rule96_id2146_at_idx8070 264alignment: 2 265legalized: true 266regBankSelected: true 267tracksRegLiveness: true 268registers: 269 - { id: 0, class: fpr } 270 - { id: 1, class: gpr } 271 - { id: 2, class: gpr } 272liveins: 273 - { reg: '$x0', virtual-reg: '%2' } 274body: | 275 bb.0.entry: 276 liveins: $x0 277 278 ; CHECK-LABEL: name: test_rule96_id2146_at_idx8070 279 ; CHECK: liveins: $x0 280 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 281 ; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load 1) 282 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[LDRBui]] 283 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY2]], 0, 0 284 ; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]] 285 %2:gpr(p0) = COPY $x0 286 %0:fpr(s1) = G_LOAD %2(p0) :: (load 1) 287 %1:gpr(s32) = G_ZEXT %0(s1) 288 $noreg = PATCHABLE_RET %1(s32) 289 290... 291--- 292name: test_rule129_id2130_at_idx10828 293alignment: 2 294legalized: true 295regBankSelected: true 296tracksRegLiveness: true 297registers: 298 - { id: 0, class: fpr } 299 - { id: 1, class: fpr } 300liveins: 301 - { reg: '$d0', virtual-reg: '%1' } 302body: | 303 bb.0.entry: 304 liveins: $d0 305 306 ; CHECK-LABEL: name: test_rule129_id2130_at_idx10828 307 ; CHECK: liveins: $d0 308 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 309 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 310 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) 311 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]] 312 %1:fpr(p0) = COPY $d0 313 %0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load 8) 314 $noreg = PATCHABLE_RET %0(<8 x s8>) 315 316... 317--- 318name: test_rule130_id2131_at_idx10884 319alignment: 2 320legalized: true 321regBankSelected: true 322tracksRegLiveness: true 323registers: 324 - { id: 0, class: fpr } 325 - { id: 1, class: fpr } 326liveins: 327 - { reg: '$d0', virtual-reg: '%1' } 328body: | 329 bb.0.entry: 330 liveins: $d0 331 332 ; CHECK-LABEL: name: test_rule130_id2131_at_idx10884 333 ; CHECK: liveins: $d0 334 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 335 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 336 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load 8) 337 ; CHECK: $noreg = PATCHABLE_RET [[LDRDui]] 338 %1:fpr(p0) = COPY $d0 339 %0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load 8) 340 $noreg = PATCHABLE_RET %0(<4 x s16>) 341 342... 343--- 344name: test_rule135_id2136_at_idx11160 345alignment: 2 346legalized: true 347regBankSelected: true 348tracksRegLiveness: true 349registers: 350 - { id: 0, class: fpr } 351 - { id: 1, class: fpr } 352liveins: 353 - { reg: '$d0', virtual-reg: '%1' } 354body: | 355 bb.0.entry: 356 liveins: $d0 357 358 ; CHECK-LABEL: name: test_rule135_id2136_at_idx11160 359 ; CHECK: liveins: $d0 360 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 361 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 362 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) 363 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 364 %1:fpr(p0) = COPY $d0 365 %0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load 16) 366 $noreg = PATCHABLE_RET %0(<4 x s32>) 367 368... 369--- 370name: test_rule136_id2137_at_idx11216 371alignment: 2 372legalized: true 373regBankSelected: true 374tracksRegLiveness: true 375registers: 376 - { id: 0, class: fpr } 377 - { id: 1, class: fpr } 378liveins: 379 - { reg: '$d0', virtual-reg: '%1' } 380body: | 381 bb.0.entry: 382 liveins: $d0 383 384 ; CHECK-LABEL: name: test_rule136_id2137_at_idx11216 385 ; CHECK: liveins: $d0 386 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 387 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 388 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) 389 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 390 %1:fpr(p0) = COPY $d0 391 %0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load 16) 392 $noreg = PATCHABLE_RET %0(<2 x s64>) 393 394... 395--- 396name: test_rule137_id2138_at_idx11272 397alignment: 2 398legalized: true 399regBankSelected: true 400tracksRegLiveness: true 401registers: 402 - { id: 0, class: fpr } 403 - { id: 1, class: fpr } 404liveins: 405 - { reg: '$d0', virtual-reg: '%1' } 406body: | 407 bb.0.entry: 408 liveins: $d0 409 410 ; CHECK-LABEL: name: test_rule137_id2138_at_idx11272 411 ; CHECK: liveins: $d0 412 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 413 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 414 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) 415 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 416 %1:fpr(p0) = COPY $d0 417 %0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load 16) 418 $noreg = PATCHABLE_RET %0(<16 x s8>) 419 420... 421--- 422name: test_rule138_id2139_at_idx11328 423alignment: 2 424legalized: true 425regBankSelected: true 426tracksRegLiveness: true 427registers: 428 - { id: 0, class: fpr } 429 - { id: 1, class: fpr } 430liveins: 431 - { reg: '$d0', virtual-reg: '%1' } 432body: | 433 bb.0.entry: 434 liveins: $d0 435 436 ; CHECK-LABEL: name: test_rule138_id2139_at_idx11328 437 ; CHECK: liveins: $d0 438 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 439 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]] 440 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load 16) 441 ; CHECK: $noreg = PATCHABLE_RET [[LDRQui]] 442 %1:fpr(p0) = COPY $d0 443 %0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load 16) 444 $noreg = PATCHABLE_RET %0(<8 x s16>) 445 446... 447--- 448name: test_rule339_id2369_at_idx26608 449alignment: 2 450legalized: true 451regBankSelected: true 452tracksRegLiveness: true 453registers: 454 - { id: 0, class: fpr } 455 - { id: 1, class: fpr } 456 - { id: 2, class: fpr } 457 - { id: 3, class: fpr } 458 - { id: 4, class: fpr } 459 - { id: 5, class: fpr } 460liveins: 461 - { reg: '$s0', virtual-reg: '%3' } 462 - { reg: '$s1', virtual-reg: '%4' } 463 - { reg: '$s2', virtual-reg: '%5' } 464body: | 465 bb.0.entry: 466 liveins: $s0, $s1, $s2 467 468 ; CHECK-LABEL: name: test_rule339_id2369_at_idx26608 469 ; CHECK: liveins: $s0, $s1, $s2 470 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 471 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 472 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 473 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]] 474 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 475 %5:fpr(s32) = COPY $s2 476 %4:fpr(s32) = COPY $s1 477 %3:fpr(s32) = COPY $s0 478 %1:fpr(s32) = G_FNEG %5 479 %0:fpr(s32) = G_FNEG %4 480 %2:fpr(s32) = G_FMA %0, %3, %1 481 $noreg = PATCHABLE_RET %2(s32) 482 483... 484--- 485name: test_rule340_id2370_at_idx26714 486alignment: 2 487legalized: true 488regBankSelected: true 489tracksRegLiveness: true 490registers: 491 - { id: 0, class: fpr } 492 - { id: 1, class: fpr } 493 - { id: 2, class: fpr } 494 - { id: 3, class: fpr } 495 - { id: 4, class: fpr } 496 - { id: 5, class: fpr } 497liveins: 498 - { reg: '$d0', virtual-reg: '%3' } 499 - { reg: '$d1', virtual-reg: '%4' } 500 - { reg: '$d2', virtual-reg: '%5' } 501body: | 502 bb.0.entry: 503 liveins: $d0, $d1, $d2 504 505 ; CHECK-LABEL: name: test_rule340_id2370_at_idx26714 506 ; CHECK: liveins: $d0, $d1, $d2 507 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 508 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 509 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 510 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]] 511 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 512 %5:fpr(s64) = COPY $d2 513 %4:fpr(s64) = COPY $d1 514 %3:fpr(s64) = COPY $d0 515 %1:fpr(s64) = G_FNEG %5 516 %0:fpr(s64) = G_FNEG %4 517 %2:fpr(s64) = G_FMA %0, %3, %1 518 $noreg = PATCHABLE_RET %2(s64) 519 520... 521--- 522name: test_rule341_id2371_at_idx26820 523alignment: 2 524legalized: true 525regBankSelected: true 526tracksRegLiveness: true 527registers: 528 - { id: 0, class: fpr } 529 - { id: 1, class: fpr } 530 - { id: 2, class: fpr } 531 - { id: 3, class: fpr } 532 - { id: 4, class: fpr } 533 - { id: 5, class: fpr } 534liveins: 535 - { reg: '$s0', virtual-reg: '%3' } 536 - { reg: '$s1', virtual-reg: '%4' } 537 - { reg: '$s2', virtual-reg: '%5' } 538body: | 539 bb.0.entry: 540 liveins: $s0, $s1, $s2 541 542 ; CHECK-LABEL: name: test_rule341_id2371_at_idx26820 543 ; CHECK: liveins: $s0, $s1, $s2 544 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 545 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 546 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 547 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] 548 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 549 %5:fpr(s32) = COPY $s2 550 %4:fpr(s32) = COPY $s1 551 %3:fpr(s32) = COPY $s0 552 %1:fpr(s32) = G_FNEG %5 553 %0:fpr(s32) = G_FNEG %4 554 %2:fpr(s32) = G_FMA %3, %0, %1 555 $noreg = PATCHABLE_RET %2(s32) 556 557... 558--- 559name: test_rule342_id2372_at_idx26926 560alignment: 2 561legalized: true 562regBankSelected: true 563tracksRegLiveness: true 564registers: 565 - { id: 0, class: fpr } 566 - { id: 1, class: fpr } 567 - { id: 2, class: fpr } 568 - { id: 3, class: fpr } 569 - { id: 4, class: fpr } 570 - { id: 5, class: fpr } 571liveins: 572 - { reg: '$d0', virtual-reg: '%3' } 573 - { reg: '$d1', virtual-reg: '%4' } 574 - { reg: '$d2', virtual-reg: '%5' } 575body: | 576 bb.0.entry: 577 liveins: $d0, $d1, $d2 578 579 ; CHECK-LABEL: name: test_rule342_id2372_at_idx26926 580 ; CHECK: liveins: $d0, $d1, $d2 581 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 582 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 583 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 584 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] 585 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 586 %5:fpr(s64) = COPY $d2 587 %4:fpr(s64) = COPY $d1 588 %3:fpr(s64) = COPY $d0 589 %1:fpr(s64) = G_FNEG %5 590 %0:fpr(s64) = G_FNEG %4 591 %2:fpr(s64) = G_FMA %3, %0, %1 592 $noreg = PATCHABLE_RET %2(s64) 593 594... 595--- 596name: test_rule343_id1266_at_idx27032 597alignment: 2 598legalized: true 599regBankSelected: true 600tracksRegLiveness: true 601registers: 602 - { id: 0, class: fpr } 603 - { id: 1, class: fpr } 604 - { id: 2, class: fpr } 605 - { id: 3, class: fpr } 606 - { id: 4, class: fpr } 607liveins: 608 - { reg: '$d0', virtual-reg: '%3' } 609 - { reg: '$d1', virtual-reg: '%4' } 610body: | 611 bb.0.entry: 612 liveins: $d0, $d1 613 614 ; CHECK-LABEL: name: test_rule343_id1266_at_idx27032 615 ; CHECK: liveins: $d0, $d1 616 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 617 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 618 ; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]] 619 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]] 620 %4:fpr(<8 x s8>) = COPY $d1 621 %3:fpr(<8 x s8>) = COPY $d0 622 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) 623 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 624 %2:fpr(<8 x s16>) = G_ADD %0, %1 625 $noreg = PATCHABLE_RET %2(<8 x s16>) 626 627... 628--- 629name: test_rule344_id1268_at_idx27128 630alignment: 2 631legalized: true 632regBankSelected: true 633tracksRegLiveness: true 634registers: 635 - { id: 0, class: fpr } 636 - { id: 1, class: fpr } 637 - { id: 2, class: fpr } 638 - { id: 3, class: fpr } 639 - { id: 4, class: fpr } 640liveins: 641 - { reg: '$d0', virtual-reg: '%3' } 642 - { reg: '$d1', virtual-reg: '%4' } 643body: | 644 bb.0.entry: 645 liveins: $d0, $d1 646 647 ; CHECK-LABEL: name: test_rule344_id1268_at_idx27128 648 ; CHECK: liveins: $d0, $d1 649 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 650 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 651 ; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]] 652 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]] 653 %4:fpr(<4 x s16>) = COPY $d1 654 %3:fpr(<4 x s16>) = COPY $d0 655 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) 656 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 657 %2:fpr(<4 x s32>) = G_ADD %0, %1 658 $noreg = PATCHABLE_RET %2(<4 x s32>) 659 660... 661--- 662name: test_rule345_id1270_at_idx27224 663alignment: 2 664legalized: true 665regBankSelected: true 666tracksRegLiveness: true 667registers: 668 - { id: 0, class: fpr } 669 - { id: 1, class: fpr } 670 - { id: 2, class: fpr } 671 - { id: 3, class: fpr } 672 - { id: 4, class: fpr } 673liveins: 674 - { reg: '$d0', virtual-reg: '%3' } 675 - { reg: '$d1', virtual-reg: '%4' } 676body: | 677 bb.0.entry: 678 liveins: $d0, $d1 679 680 ; CHECK-LABEL: name: test_rule345_id1270_at_idx27224 681 ; CHECK: liveins: $d0, $d1 682 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 683 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 684 ; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]] 685 ; CHECK: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]] 686 %4:fpr(<2 x s32>) = COPY $d1 687 %3:fpr(<2 x s32>) = COPY $d0 688 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) 689 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 690 %2:fpr(<2 x s64>) = G_ADD %0, %1 691 $noreg = PATCHABLE_RET %2(<2 x s64>) 692 693... 694--- 695name: test_rule346_id1326_at_idx27320 696alignment: 2 697legalized: true 698regBankSelected: true 699tracksRegLiveness: true 700registers: 701 - { id: 0, class: fpr } 702 - { id: 1, class: fpr } 703 - { id: 2, class: fpr } 704 - { id: 3, class: fpr } 705 - { id: 4, class: fpr } 706liveins: 707 - { reg: '$d0', virtual-reg: '%3' } 708 - { reg: '$d1', virtual-reg: '%4' } 709body: | 710 bb.0.entry: 711 liveins: $d0, $d1 712 713 ; CHECK-LABEL: name: test_rule346_id1326_at_idx27320 714 ; CHECK: liveins: $d0, $d1 715 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 716 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 717 ; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]] 718 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]] 719 %4:fpr(<8 x s8>) = COPY $d1 720 %3:fpr(<8 x s8>) = COPY $d0 721 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) 722 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 723 %2:fpr(<8 x s16>) = G_ADD %0, %1 724 $noreg = PATCHABLE_RET %2(<8 x s16>) 725 726... 727--- 728name: test_rule347_id1328_at_idx27416 729alignment: 2 730legalized: true 731regBankSelected: true 732tracksRegLiveness: true 733registers: 734 - { id: 0, class: fpr } 735 - { id: 1, class: fpr } 736 - { id: 2, class: fpr } 737 - { id: 3, class: fpr } 738 - { id: 4, class: fpr } 739liveins: 740 - { reg: '$d0', virtual-reg: '%3' } 741 - { reg: '$d1', virtual-reg: '%4' } 742body: | 743 bb.0.entry: 744 liveins: $d0, $d1 745 746 ; CHECK-LABEL: name: test_rule347_id1328_at_idx27416 747 ; CHECK: liveins: $d0, $d1 748 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 749 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 750 ; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]] 751 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]] 752 %4:fpr(<4 x s16>) = COPY $d1 753 %3:fpr(<4 x s16>) = COPY $d0 754 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) 755 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 756 %2:fpr(<4 x s32>) = G_ADD %0, %1 757 $noreg = PATCHABLE_RET %2(<4 x s32>) 758 759... 760--- 761name: test_rule348_id1330_at_idx27512 762alignment: 2 763legalized: true 764regBankSelected: true 765tracksRegLiveness: true 766registers: 767 - { id: 0, class: fpr } 768 - { id: 1, class: fpr } 769 - { id: 2, class: fpr } 770 - { id: 3, class: fpr } 771 - { id: 4, class: fpr } 772liveins: 773 - { reg: '$d0', virtual-reg: '%3' } 774 - { reg: '$d1', virtual-reg: '%4' } 775body: | 776 bb.0.entry: 777 liveins: $d0, $d1 778 779 ; CHECK-LABEL: name: test_rule348_id1330_at_idx27512 780 ; CHECK: liveins: $d0, $d1 781 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 782 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 783 ; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]] 784 ; CHECK: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]] 785 %4:fpr(<2 x s32>) = COPY $d1 786 %3:fpr(<2 x s32>) = COPY $d0 787 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) 788 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 789 %2:fpr(<2 x s64>) = G_ADD %0, %1 790 $noreg = PATCHABLE_RET %2(<2 x s64>) 791 792... 793--- 794name: test_rule349_id1308_at_idx27608 795alignment: 2 796legalized: true 797regBankSelected: true 798tracksRegLiveness: true 799registers: 800 - { id: 0, class: fpr } 801 - { id: 1, class: fpr } 802 - { id: 2, class: fpr } 803 - { id: 3, class: fpr } 804 - { id: 4, class: fpr } 805liveins: 806 - { reg: '$d0', virtual-reg: '%3' } 807 - { reg: '$d1', virtual-reg: '%4' } 808body: | 809 bb.0.entry: 810 liveins: $d0, $d1 811 812 ; CHECK-LABEL: name: test_rule349_id1308_at_idx27608 813 ; CHECK: liveins: $d0, $d1 814 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 815 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 816 ; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]] 817 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]] 818 %4:fpr(<8 x s8>) = COPY $d1 819 %3:fpr(<8 x s8>) = COPY $d0 820 %1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>) 821 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 822 %2:fpr(<8 x s16>) = G_SUB %0, %1 823 $noreg = PATCHABLE_RET %2(<8 x s16>) 824 825... 826--- 827name: test_rule350_id1310_at_idx27704 828alignment: 2 829legalized: true 830regBankSelected: true 831tracksRegLiveness: true 832registers: 833 - { id: 0, class: fpr } 834 - { id: 1, class: fpr } 835 - { id: 2, class: fpr } 836 - { id: 3, class: fpr } 837 - { id: 4, class: fpr } 838liveins: 839 - { reg: '$d0', virtual-reg: '%3' } 840 - { reg: '$d1', virtual-reg: '%4' } 841body: | 842 bb.0.entry: 843 liveins: $d0, $d1 844 845 ; CHECK-LABEL: name: test_rule350_id1310_at_idx27704 846 ; CHECK: liveins: $d0, $d1 847 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 848 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 849 ; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]] 850 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]] 851 %4:fpr(<4 x s16>) = COPY $d1 852 %3:fpr(<4 x s16>) = COPY $d0 853 %1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>) 854 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 855 %2:fpr(<4 x s32>) = G_SUB %0, %1 856 $noreg = PATCHABLE_RET %2(<4 x s32>) 857 858... 859--- 860name: test_rule351_id1312_at_idx27800 861alignment: 2 862legalized: true 863regBankSelected: true 864tracksRegLiveness: true 865registers: 866 - { id: 0, class: fpr } 867 - { id: 1, class: fpr } 868 - { id: 2, class: fpr } 869 - { id: 3, class: fpr } 870 - { id: 4, class: fpr } 871liveins: 872 - { reg: '$d0', virtual-reg: '%3' } 873 - { reg: '$d1', virtual-reg: '%4' } 874body: | 875 bb.0.entry: 876 liveins: $d0, $d1 877 878 ; CHECK-LABEL: name: test_rule351_id1312_at_idx27800 879 ; CHECK: liveins: $d0, $d1 880 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 881 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 882 ; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]] 883 ; CHECK: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]] 884 %4:fpr(<2 x s32>) = COPY $d1 885 %3:fpr(<2 x s32>) = COPY $d0 886 %1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>) 887 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 888 %2:fpr(<2 x s64>) = G_SUB %0, %1 889 $noreg = PATCHABLE_RET %2(<2 x s64>) 890 891... 892--- 893name: test_rule352_id1356_at_idx27896 894alignment: 2 895legalized: true 896regBankSelected: true 897tracksRegLiveness: true 898registers: 899 - { id: 0, class: fpr } 900 - { id: 1, class: fpr } 901 - { id: 2, class: fpr } 902 - { id: 3, class: fpr } 903 - { id: 4, class: fpr } 904liveins: 905 - { reg: '$d0', virtual-reg: '%3' } 906 - { reg: '$d1', virtual-reg: '%4' } 907body: | 908 bb.0.entry: 909 liveins: $d0, $d1 910 911 ; CHECK-LABEL: name: test_rule352_id1356_at_idx27896 912 ; CHECK: liveins: $d0, $d1 913 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 914 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 915 ; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]] 916 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]] 917 %4:fpr(<8 x s8>) = COPY $d1 918 %3:fpr(<8 x s8>) = COPY $d0 919 %1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>) 920 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 921 %2:fpr(<8 x s16>) = G_SUB %0, %1 922 $noreg = PATCHABLE_RET %2(<8 x s16>) 923 924... 925--- 926name: test_rule353_id1358_at_idx27992 927alignment: 2 928legalized: true 929regBankSelected: true 930tracksRegLiveness: true 931registers: 932 - { id: 0, class: fpr } 933 - { id: 1, class: fpr } 934 - { id: 2, class: fpr } 935 - { id: 3, class: fpr } 936 - { id: 4, class: fpr } 937liveins: 938 - { reg: '$d0', virtual-reg: '%3' } 939 - { reg: '$d1', virtual-reg: '%4' } 940body: | 941 bb.0.entry: 942 liveins: $d0, $d1 943 944 ; CHECK-LABEL: name: test_rule353_id1358_at_idx27992 945 ; CHECK: liveins: $d0, $d1 946 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 947 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 948 ; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]] 949 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]] 950 %4:fpr(<4 x s16>) = COPY $d1 951 %3:fpr(<4 x s16>) = COPY $d0 952 %1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>) 953 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 954 %2:fpr(<4 x s32>) = G_SUB %0, %1 955 $noreg = PATCHABLE_RET %2(<4 x s32>) 956 957... 958--- 959name: test_rule354_id1360_at_idx28088 960alignment: 2 961legalized: true 962regBankSelected: true 963tracksRegLiveness: true 964registers: 965 - { id: 0, class: fpr } 966 - { id: 1, class: fpr } 967 - { id: 2, class: fpr } 968 - { id: 3, class: fpr } 969 - { id: 4, class: fpr } 970liveins: 971 - { reg: '$d0', virtual-reg: '%3' } 972 - { reg: '$d1', virtual-reg: '%4' } 973body: | 974 bb.0.entry: 975 liveins: $d0, $d1 976 977 ; CHECK-LABEL: name: test_rule354_id1360_at_idx28088 978 ; CHECK: liveins: $d0, $d1 979 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 980 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 981 ; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]] 982 ; CHECK: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]] 983 %4:fpr(<2 x s32>) = COPY $d1 984 %3:fpr(<2 x s32>) = COPY $d0 985 %1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>) 986 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 987 %2:fpr(<2 x s64>) = G_SUB %0, %1 988 $noreg = PATCHABLE_RET %2(<2 x s64>) 989 990... 991--- 992name: test_rule928_id2367_at_idx60019 993alignment: 2 994legalized: true 995regBankSelected: true 996tracksRegLiveness: true 997registers: 998 - { id: 0, class: fpr } 999 - { id: 1, class: fpr } 1000 - { id: 2, class: fpr } 1001 - { id: 3, class: fpr } 1002 - { id: 4, class: fpr } 1003liveins: 1004 - { reg: '$s0', virtual-reg: '%2' } 1005 - { reg: '$s1', virtual-reg: '%3' } 1006 - { reg: '$s2', virtual-reg: '%4' } 1007body: | 1008 bb.0.entry: 1009 liveins: $s0, $s1, $s2 1010 1011 ; CHECK-LABEL: name: test_rule928_id2367_at_idx60019 1012 ; CHECK: liveins: $s0, $s1, $s2 1013 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1014 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1015 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1016 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]] 1017 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]] 1018 %4:fpr(s32) = COPY $s2 1019 %3:fpr(s32) = COPY $s1 1020 %2:fpr(s32) = COPY $s0 1021 %0:fpr(s32) = G_FNEG %4 1022 %1:fpr(s32) = G_FMA %0, %2, %3 1023 $noreg = PATCHABLE_RET %1(s32) 1024 1025... 1026--- 1027name: test_rule929_id2368_at_idx60105 1028alignment: 2 1029legalized: true 1030regBankSelected: true 1031tracksRegLiveness: true 1032registers: 1033 - { id: 0, class: fpr } 1034 - { id: 1, class: fpr } 1035 - { id: 2, class: fpr } 1036 - { id: 3, class: fpr } 1037 - { id: 4, class: fpr } 1038liveins: 1039 - { reg: '$d0', virtual-reg: '%2' } 1040 - { reg: '$d1', virtual-reg: '%3' } 1041 - { reg: '$d2', virtual-reg: '%4' } 1042body: | 1043 bb.0.entry: 1044 liveins: $d0, $d1, $d2 1045 1046 ; CHECK-LABEL: name: test_rule929_id2368_at_idx60105 1047 ; CHECK: liveins: $d0, $d1, $d2 1048 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1049 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1050 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1051 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]] 1052 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]] 1053 %4:fpr(s64) = COPY $d2 1054 %3:fpr(s64) = COPY $d1 1055 %2:fpr(s64) = COPY $d0 1056 %0:fpr(s64) = G_FNEG %4 1057 %1:fpr(s64) = G_FMA %0, %2, %3 1058 $noreg = PATCHABLE_RET %1(s64) 1059 1060... 1061--- 1062name: test_rule930_id2446_at_idx60191 1063alignment: 2 1064legalized: true 1065regBankSelected: true 1066tracksRegLiveness: true 1067registers: 1068 - { id: 0, class: fpr } 1069 - { id: 1, class: fpr } 1070 - { id: 2, class: fpr } 1071 - { id: 3, class: fpr } 1072 - { id: 4, class: fpr } 1073liveins: 1074 - { reg: '$d0', virtual-reg: '%2' } 1075 - { reg: '$d1', virtual-reg: '%3' } 1076 - { reg: '$d2', virtual-reg: '%4' } 1077body: | 1078 bb.0.entry: 1079 liveins: $d0, $d1, $d2 1080 1081 ; CHECK-LABEL: name: test_rule930_id2446_at_idx60191 1082 ; CHECK: liveins: $d0, $d1, $d2 1083 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1084 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1085 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1086 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY]], [[COPY2]] 1087 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] 1088 %4:fpr(<2 x s32>) = COPY $d2 1089 %3:fpr(<2 x s32>) = COPY $d1 1090 %2:fpr(<2 x s32>) = COPY $d0 1091 %0:fpr(<2 x s32>) = G_FNEG %4 1092 %1:fpr(<2 x s32>) = G_FMA %0, %2, %3 1093 $noreg = PATCHABLE_RET %1(<2 x s32>) 1094 1095... 1096--- 1097name: test_rule931_id2447_at_idx60277 1098alignment: 2 1099legalized: true 1100regBankSelected: true 1101tracksRegLiveness: true 1102registers: 1103 - { id: 0, class: fpr } 1104 - { id: 1, class: fpr } 1105 - { id: 2, class: fpr } 1106 - { id: 3, class: fpr } 1107 - { id: 4, class: fpr } 1108liveins: 1109 - { reg: '$q0', virtual-reg: '%2' } 1110 - { reg: '$q1', virtual-reg: '%3' } 1111 - { reg: '$q2', virtual-reg: '%4' } 1112body: | 1113 bb.0.entry: 1114 liveins: $q0, $q1, $q2 1115 1116 ; CHECK-LABEL: name: test_rule931_id2447_at_idx60277 1117 ; CHECK: liveins: $q0, $q1, $q2 1118 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1119 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1120 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1121 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY]], [[COPY2]] 1122 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] 1123 %4:fpr(<4 x s32>) = COPY $q2 1124 %3:fpr(<4 x s32>) = COPY $q1 1125 %2:fpr(<4 x s32>) = COPY $q0 1126 %0:fpr(<4 x s32>) = G_FNEG %4 1127 %1:fpr(<4 x s32>) = G_FMA %0, %2, %3 1128 $noreg = PATCHABLE_RET %1(<4 x s32>) 1129 1130... 1131--- 1132name: test_rule932_id2448_at_idx60363 1133alignment: 2 1134legalized: true 1135regBankSelected: true 1136tracksRegLiveness: true 1137registers: 1138 - { id: 0, class: fpr } 1139 - { id: 1, class: fpr } 1140 - { id: 2, class: fpr } 1141 - { id: 3, class: fpr } 1142 - { id: 4, class: fpr } 1143liveins: 1144 - { reg: '$q0', virtual-reg: '%2' } 1145 - { reg: '$q1', virtual-reg: '%3' } 1146 - { reg: '$q2', virtual-reg: '%4' } 1147body: | 1148 bb.0.entry: 1149 liveins: $q0, $q1, $q2 1150 1151 ; CHECK-LABEL: name: test_rule932_id2448_at_idx60363 1152 ; CHECK: liveins: $q0, $q1, $q2 1153 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1154 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1155 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1156 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY]], [[COPY2]] 1157 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] 1158 %4:fpr(<2 x s64>) = COPY $q2 1159 %3:fpr(<2 x s64>) = COPY $q1 1160 %2:fpr(<2 x s64>) = COPY $q0 1161 %0:fpr(<2 x s64>) = G_FNEG %4 1162 %1:fpr(<2 x s64>) = G_FMA %0, %2, %3 1163 $noreg = PATCHABLE_RET %1(<2 x s64>) 1164 1165... 1166--- 1167name: test_rule934_id429_at_idx60537 1168alignment: 2 1169legalized: true 1170regBankSelected: true 1171tracksRegLiveness: true 1172registers: 1173 - { id: 0, class: fpr } 1174 - { id: 1, class: fpr } 1175 - { id: 2, class: fpr } 1176 - { id: 3, class: fpr } 1177 - { id: 4, class: fpr } 1178liveins: 1179 - { reg: '$s0', virtual-reg: '%2' } 1180 - { reg: '$s1', virtual-reg: '%3' } 1181 - { reg: '$s2', virtual-reg: '%4' } 1182body: | 1183 bb.0.entry: 1184 liveins: $s0, $s1, $s2 1185 1186 ; CHECK-LABEL: name: test_rule934_id429_at_idx60537 1187 ; CHECK: liveins: $s0, $s1, $s2 1188 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1189 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1190 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1191 ; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]] 1192 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]] 1193 %4:fpr(s32) = COPY $s2 1194 %3:fpr(s32) = COPY $s1 1195 %2:fpr(s32) = COPY $s0 1196 %0:fpr(s32) = G_FNEG %4 1197 %1:fpr(s32) = G_FMA %2, %0, %3 1198 $noreg = PATCHABLE_RET %1(s32) 1199 1200... 1201--- 1202name: test_rule935_id430_at_idx60625 1203alignment: 2 1204legalized: true 1205regBankSelected: true 1206tracksRegLiveness: true 1207registers: 1208 - { id: 0, class: fpr } 1209 - { id: 1, class: fpr } 1210 - { id: 2, class: fpr } 1211 - { id: 3, class: fpr } 1212 - { id: 4, class: fpr } 1213liveins: 1214 - { reg: '$d0', virtual-reg: '%2' } 1215 - { reg: '$d1', virtual-reg: '%3' } 1216 - { reg: '$d2', virtual-reg: '%4' } 1217body: | 1218 bb.0.entry: 1219 liveins: $d0, $d1, $d2 1220 1221 ; CHECK-LABEL: name: test_rule935_id430_at_idx60625 1222 ; CHECK: liveins: $d0, $d1, $d2 1223 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1224 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1225 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1226 ; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]] 1227 ; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]] 1228 %4:fpr(s64) = COPY $d2 1229 %3:fpr(s64) = COPY $d1 1230 %2:fpr(s64) = COPY $d0 1231 %0:fpr(s64) = G_FNEG %4 1232 %1:fpr(s64) = G_FMA %2, %0, %3 1233 $noreg = PATCHABLE_RET %1(s64) 1234 1235... 1236--- 1237name: test_rule938_id899_at_idx60889 1238alignment: 2 1239legalized: true 1240regBankSelected: true 1241tracksRegLiveness: true 1242registers: 1243 - { id: 0, class: fpr } 1244 - { id: 1, class: fpr } 1245 - { id: 2, class: fpr } 1246 - { id: 3, class: fpr } 1247 - { id: 4, class: fpr } 1248liveins: 1249 - { reg: '$d0', virtual-reg: '%2' } 1250 - { reg: '$d1', virtual-reg: '%3' } 1251 - { reg: '$d2', virtual-reg: '%4' } 1252body: | 1253 bb.0.entry: 1254 liveins: $d0, $d1, $d2 1255 1256 ; CHECK-LABEL: name: test_rule938_id899_at_idx60889 1257 ; CHECK: liveins: $d0, $d1, $d2 1258 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1259 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1260 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1261 ; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]] 1262 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]] 1263 %4:fpr(<2 x s32>) = COPY $d2 1264 %3:fpr(<2 x s32>) = COPY $d1 1265 %2:fpr(<2 x s32>) = COPY $d0 1266 %0:fpr(<2 x s32>) = G_FNEG %4 1267 %1:fpr(<2 x s32>) = G_FMA %2, %0, %3 1268 $noreg = PATCHABLE_RET %1(<2 x s32>) 1269 1270... 1271--- 1272name: test_rule939_id900_at_idx60977 1273alignment: 2 1274legalized: true 1275regBankSelected: true 1276tracksRegLiveness: true 1277registers: 1278 - { id: 0, class: fpr } 1279 - { id: 1, class: fpr } 1280 - { id: 2, class: fpr } 1281 - { id: 3, class: fpr } 1282 - { id: 4, class: fpr } 1283liveins: 1284 - { reg: '$q0', virtual-reg: '%2' } 1285 - { reg: '$q1', virtual-reg: '%3' } 1286 - { reg: '$q2', virtual-reg: '%4' } 1287body: | 1288 bb.0.entry: 1289 liveins: $q0, $q1, $q2 1290 1291 ; CHECK-LABEL: name: test_rule939_id900_at_idx60977 1292 ; CHECK: liveins: $q0, $q1, $q2 1293 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1294 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1295 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1296 ; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]] 1297 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]] 1298 %4:fpr(<4 x s32>) = COPY $q2 1299 %3:fpr(<4 x s32>) = COPY $q1 1300 %2:fpr(<4 x s32>) = COPY $q0 1301 %0:fpr(<4 x s32>) = G_FNEG %4 1302 %1:fpr(<4 x s32>) = G_FMA %2, %0, %3 1303 $noreg = PATCHABLE_RET %1(<4 x s32>) 1304 1305... 1306--- 1307name: test_rule940_id901_at_idx61065 1308alignment: 2 1309legalized: true 1310regBankSelected: true 1311tracksRegLiveness: true 1312registers: 1313 - { id: 0, class: fpr } 1314 - { id: 1, class: fpr } 1315 - { id: 2, class: fpr } 1316 - { id: 3, class: fpr } 1317 - { id: 4, class: fpr } 1318liveins: 1319 - { reg: '$q0', virtual-reg: '%2' } 1320 - { reg: '$q1', virtual-reg: '%3' } 1321 - { reg: '$q2', virtual-reg: '%4' } 1322body: | 1323 bb.0.entry: 1324 liveins: $q0, $q1, $q2 1325 1326 ; CHECK-LABEL: name: test_rule940_id901_at_idx61065 1327 ; CHECK: liveins: $q0, $q1, $q2 1328 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1329 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1330 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1331 ; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]] 1332 ; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]] 1333 %4:fpr(<2 x s64>) = COPY $q2 1334 %3:fpr(<2 x s64>) = COPY $q1 1335 %2:fpr(<2 x s64>) = COPY $q0 1336 %0:fpr(<2 x s64>) = G_FNEG %4 1337 %1:fpr(<2 x s64>) = G_FMA %2, %0, %3 1338 $noreg = PATCHABLE_RET %1(<2 x s64>) 1339 1340... 1341--- 1342name: test_rule942_id435_at_idx61241 1343alignment: 2 1344legalized: true 1345regBankSelected: true 1346tracksRegLiveness: true 1347registers: 1348 - { id: 0, class: fpr } 1349 - { id: 1, class: fpr } 1350 - { id: 2, class: fpr } 1351 - { id: 3, class: fpr } 1352 - { id: 4, class: fpr } 1353liveins: 1354 - { reg: '$s0', virtual-reg: '%2' } 1355 - { reg: '$s1', virtual-reg: '%3' } 1356 - { reg: '$s2', virtual-reg: '%4' } 1357body: | 1358 bb.0.entry: 1359 liveins: $s0, $s1, $s2 1360 1361 ; CHECK-LABEL: name: test_rule942_id435_at_idx61241 1362 ; CHECK: liveins: $s0, $s1, $s2 1363 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 1364 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1365 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 1366 ; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]] 1367 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]] 1368 %4:fpr(s32) = COPY $s2 1369 %3:fpr(s32) = COPY $s1 1370 %2:fpr(s32) = COPY $s0 1371 %0:fpr(s32) = G_FNEG %4 1372 %1:fpr(s32) = G_FMA %2, %3, %0 1373 $noreg = PATCHABLE_RET %1(s32) 1374 1375... 1376--- 1377name: test_rule943_id436_at_idx61329 1378alignment: 2 1379legalized: true 1380regBankSelected: true 1381tracksRegLiveness: true 1382registers: 1383 - { id: 0, class: fpr } 1384 - { id: 1, class: fpr } 1385 - { id: 2, class: fpr } 1386 - { id: 3, class: fpr } 1387 - { id: 4, class: fpr } 1388liveins: 1389 - { reg: '$d0', virtual-reg: '%2' } 1390 - { reg: '$d1', virtual-reg: '%3' } 1391 - { reg: '$d2', virtual-reg: '%4' } 1392body: | 1393 bb.0.entry: 1394 liveins: $d0, $d1, $d2 1395 1396 ; CHECK-LABEL: name: test_rule943_id436_at_idx61329 1397 ; CHECK: liveins: $d0, $d1, $d2 1398 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1399 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1400 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1401 ; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]] 1402 ; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]] 1403 %4:fpr(s64) = COPY $d2 1404 %3:fpr(s64) = COPY $d1 1405 %2:fpr(s64) = COPY $d0 1406 %0:fpr(s64) = G_FNEG %4 1407 %1:fpr(s64) = G_FMA %2, %3, %0 1408 $noreg = PATCHABLE_RET %1(s64) 1409 1410... 1411--- 1412name: test_rule944_id3803_at_idx61417 1413alignment: 2 1414legalized: true 1415regBankSelected: true 1416tracksRegLiveness: true 1417registers: 1418 - { id: 0, class: fpr } 1419 - { id: 1, class: fpr } 1420 - { id: 2, class: fpr } 1421 - { id: 3, class: fpr } 1422 - { id: 4, class: fpr } 1423liveins: 1424 - { reg: '$d0', virtual-reg: '%2' } 1425 - { reg: '$d1', virtual-reg: '%3' } 1426 - { reg: '$d2', virtual-reg: '%4' } 1427body: | 1428 bb.0.entry: 1429 liveins: $d0, $d1, $d2 1430 1431 ; CHECK-LABEL: name: test_rule944_id3803_at_idx61417 1432 ; CHECK: liveins: $d0, $d1, $d2 1433 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1434 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1435 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1436 ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]] 1437 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]] 1438 %4:fpr(<8 x s8>) = COPY $d2 1439 %3:fpr(<8 x s8>) = COPY $d1 1440 %2:fpr(<8 x s8>) = COPY $d0 1441 %0:fpr(<8 x s8>) = G_MUL %3, %4 1442 %1:fpr(<8 x s8>) = G_ADD %0, %2 1443 $noreg = PATCHABLE_RET %1(<8 x s8>) 1444 1445... 1446--- 1447name: test_rule945_id3804_at_idx61505 1448alignment: 2 1449legalized: true 1450regBankSelected: true 1451tracksRegLiveness: true 1452registers: 1453 - { id: 0, class: fpr } 1454 - { id: 1, class: fpr } 1455 - { id: 2, class: fpr } 1456 - { id: 3, class: fpr } 1457 - { id: 4, class: fpr } 1458liveins: 1459 - { reg: '$q0', virtual-reg: '%2' } 1460 - { reg: '$q1', virtual-reg: '%3' } 1461 - { reg: '$q2', virtual-reg: '%4' } 1462body: | 1463 bb.0.entry: 1464 liveins: $q0, $q1, $q2 1465 1466 ; CHECK-LABEL: name: test_rule945_id3804_at_idx61505 1467 ; CHECK: liveins: $q0, $q1, $q2 1468 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1469 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1470 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1471 ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]] 1472 ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]] 1473 %4:fpr(<16 x s8>) = COPY $q2 1474 %3:fpr(<16 x s8>) = COPY $q1 1475 %2:fpr(<16 x s8>) = COPY $q0 1476 %0:fpr(<16 x s8>) = G_MUL %3, %4 1477 %1:fpr(<16 x s8>) = G_ADD %0, %2 1478 $noreg = PATCHABLE_RET %1(<16 x s8>) 1479 1480... 1481--- 1482name: test_rule946_id3805_at_idx61593 1483alignment: 2 1484legalized: true 1485regBankSelected: true 1486tracksRegLiveness: true 1487registers: 1488 - { id: 0, class: fpr } 1489 - { id: 1, class: fpr } 1490 - { id: 2, class: fpr } 1491 - { id: 3, class: fpr } 1492 - { id: 4, class: fpr } 1493liveins: 1494 - { reg: '$d0', virtual-reg: '%2' } 1495 - { reg: '$d1', virtual-reg: '%3' } 1496 - { reg: '$d2', virtual-reg: '%4' } 1497body: | 1498 bb.0.entry: 1499 liveins: $d0, $d1, $d2 1500 1501 ; CHECK-LABEL: name: test_rule946_id3805_at_idx61593 1502 ; CHECK: liveins: $d0, $d1, $d2 1503 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1504 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1505 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1506 ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]] 1507 ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]] 1508 %4:fpr(<4 x s16>) = COPY $d2 1509 %3:fpr(<4 x s16>) = COPY $d1 1510 %2:fpr(<4 x s16>) = COPY $d0 1511 %0:fpr(<4 x s16>) = G_MUL %3, %4 1512 %1:fpr(<4 x s16>) = G_ADD %0, %2 1513 $noreg = PATCHABLE_RET %1(<4 x s16>) 1514 1515... 1516--- 1517name: test_rule947_id3806_at_idx61681 1518alignment: 2 1519legalized: true 1520regBankSelected: true 1521tracksRegLiveness: true 1522registers: 1523 - { id: 0, class: fpr } 1524 - { id: 1, class: fpr } 1525 - { id: 2, class: fpr } 1526 - { id: 3, class: fpr } 1527 - { id: 4, class: fpr } 1528liveins: 1529 - { reg: '$q0', virtual-reg: '%2' } 1530 - { reg: '$q1', virtual-reg: '%3' } 1531 - { reg: '$q2', virtual-reg: '%4' } 1532body: | 1533 bb.0.entry: 1534 liveins: $q0, $q1, $q2 1535 1536 ; CHECK-LABEL: name: test_rule947_id3806_at_idx61681 1537 ; CHECK: liveins: $q0, $q1, $q2 1538 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1539 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1540 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1541 ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]] 1542 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]] 1543 %4:fpr(<8 x s16>) = COPY $q2 1544 %3:fpr(<8 x s16>) = COPY $q1 1545 %2:fpr(<8 x s16>) = COPY $q0 1546 %0:fpr(<8 x s16>) = G_MUL %3, %4 1547 %1:fpr(<8 x s16>) = G_ADD %0, %2 1548 $noreg = PATCHABLE_RET %1(<8 x s16>) 1549 1550... 1551--- 1552name: test_rule950_id3869_at_idx61945 1553alignment: 2 1554legalized: true 1555regBankSelected: true 1556tracksRegLiveness: true 1557registers: 1558 - { id: 0, class: fpr } 1559 - { id: 1, class: fpr } 1560 - { id: 2, class: fpr } 1561 - { id: 3, class: fpr } 1562liveins: 1563 - { reg: '$q0', virtual-reg: '%2' } 1564 - { reg: '$d0', virtual-reg: '%3' } 1565body: | 1566 bb.0.entry: 1567 liveins: $q0, $d0 1568 1569 ; CHECK-LABEL: name: test_rule950_id3869_at_idx61945 1570 ; CHECK: liveins: $q0, $d0 1571 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1572 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1573 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1574 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]] 1575 %3:fpr(<8 x s8>) = COPY $d0 1576 %2:fpr(<8 x s16>) = COPY $q0 1577 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 1578 %1:fpr(<8 x s16>) = G_ADD %0, %2 1579 $noreg = PATCHABLE_RET %1(<8 x s16>) 1580 1581... 1582--- 1583name: test_rule951_id3871_at_idx62021 1584alignment: 2 1585legalized: true 1586regBankSelected: true 1587tracksRegLiveness: true 1588registers: 1589 - { id: 0, class: fpr } 1590 - { id: 1, class: fpr } 1591 - { id: 2, class: fpr } 1592 - { id: 3, class: fpr } 1593liveins: 1594 - { reg: '$q0', virtual-reg: '%2' } 1595 - { reg: '$d0', virtual-reg: '%3' } 1596body: | 1597 bb.0.entry: 1598 liveins: $q0, $d0 1599 1600 ; CHECK-LABEL: name: test_rule951_id3871_at_idx62021 1601 ; CHECK: liveins: $q0, $d0 1602 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1603 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1604 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1605 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]] 1606 %3:fpr(<4 x s16>) = COPY $d0 1607 %2:fpr(<4 x s32>) = COPY $q0 1608 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 1609 %1:fpr(<4 x s32>) = G_ADD %0, %2 1610 $noreg = PATCHABLE_RET %1(<4 x s32>) 1611 1612... 1613--- 1614name: test_rule952_id3873_at_idx62097 1615alignment: 2 1616legalized: true 1617regBankSelected: true 1618tracksRegLiveness: true 1619registers: 1620 - { id: 0, class: fpr } 1621 - { id: 1, class: fpr } 1622 - { id: 2, class: fpr } 1623 - { id: 3, class: fpr } 1624liveins: 1625 - { reg: '$q0', virtual-reg: '%2' } 1626 - { reg: '$d0', virtual-reg: '%3' } 1627body: | 1628 bb.0.entry: 1629 liveins: $q0, $d0 1630 1631 ; CHECK-LABEL: name: test_rule952_id3873_at_idx62097 1632 ; CHECK: liveins: $q0, $d0 1633 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1634 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1635 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1636 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]] 1637 %3:fpr(<2 x s32>) = COPY $d0 1638 %2:fpr(<2 x s64>) = COPY $q0 1639 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 1640 %1:fpr(<2 x s64>) = G_ADD %0, %2 1641 $noreg = PATCHABLE_RET %1(<2 x s64>) 1642 1643... 1644--- 1645name: test_rule953_id3887_at_idx62173 1646alignment: 2 1647legalized: true 1648regBankSelected: true 1649tracksRegLiveness: true 1650registers: 1651 - { id: 0, class: fpr } 1652 - { id: 1, class: fpr } 1653 - { id: 2, class: fpr } 1654 - { id: 3, class: fpr } 1655liveins: 1656 - { reg: '$q0', virtual-reg: '%2' } 1657 - { reg: '$d0', virtual-reg: '%3' } 1658body: | 1659 bb.0.entry: 1660 liveins: $q0, $d0 1661 1662 ; CHECK-LABEL: name: test_rule953_id3887_at_idx62173 1663 ; CHECK: liveins: $q0, $d0 1664 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1665 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1666 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1667 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]] 1668 %3:fpr(<8 x s8>) = COPY $d0 1669 %2:fpr(<8 x s16>) = COPY $q0 1670 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 1671 %1:fpr(<8 x s16>) = G_ADD %0, %2 1672 $noreg = PATCHABLE_RET %1(<8 x s16>) 1673 1674... 1675--- 1676name: test_rule954_id3889_at_idx62249 1677alignment: 2 1678legalized: true 1679regBankSelected: true 1680tracksRegLiveness: true 1681registers: 1682 - { id: 0, class: fpr } 1683 - { id: 1, class: fpr } 1684 - { id: 2, class: fpr } 1685 - { id: 3, class: fpr } 1686liveins: 1687 - { reg: '$q0', virtual-reg: '%2' } 1688 - { reg: '$d0', virtual-reg: '%3' } 1689body: | 1690 bb.0.entry: 1691 liveins: $q0, $d0 1692 1693 ; CHECK-LABEL: name: test_rule954_id3889_at_idx62249 1694 ; CHECK: liveins: $q0, $d0 1695 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1696 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1697 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1698 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]] 1699 %3:fpr(<4 x s16>) = COPY $d0 1700 %2:fpr(<4 x s32>) = COPY $q0 1701 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 1702 %1:fpr(<4 x s32>) = G_ADD %0, %2 1703 $noreg = PATCHABLE_RET %1(<4 x s32>) 1704 1705... 1706--- 1707name: test_rule955_id3891_at_idx62325 1708alignment: 2 1709legalized: true 1710regBankSelected: true 1711tracksRegLiveness: true 1712registers: 1713 - { id: 0, class: fpr } 1714 - { id: 1, class: fpr } 1715 - { id: 2, class: fpr } 1716 - { id: 3, class: fpr } 1717liveins: 1718 - { reg: '$q0', virtual-reg: '%2' } 1719 - { reg: '$d0', virtual-reg: '%3' } 1720body: | 1721 bb.0.entry: 1722 liveins: $q0, $d0 1723 1724 ; CHECK-LABEL: name: test_rule955_id3891_at_idx62325 1725 ; CHECK: liveins: $q0, $d0 1726 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1727 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1728 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1729 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]] 1730 %3:fpr(<2 x s32>) = COPY $d0 1731 %2:fpr(<2 x s64>) = COPY $q0 1732 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 1733 %1:fpr(<2 x s64>) = G_ADD %0, %2 1734 $noreg = PATCHABLE_RET %1(<2 x s64>) 1735 1736... 1737--- 1738name: test_rule956_id927_at_idx62401 1739alignment: 2 1740legalized: true 1741regBankSelected: true 1742tracksRegLiveness: true 1743registers: 1744 - { id: 0, class: fpr } 1745 - { id: 1, class: fpr } 1746 - { id: 2, class: fpr } 1747 - { id: 3, class: fpr } 1748 - { id: 4, class: fpr } 1749liveins: 1750 - { reg: '$d0', virtual-reg: '%2' } 1751 - { reg: '$d1', virtual-reg: '%3' } 1752 - { reg: '$d2', virtual-reg: '%4' } 1753body: | 1754 bb.0.entry: 1755 liveins: $d0, $d1, $d2 1756 1757 ; CHECK-LABEL: name: test_rule956_id927_at_idx62401 1758 ; CHECK: liveins: $d0, $d1, $d2 1759 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1760 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1761 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1762 ; CHECK: [[MLAv8i8_:%[0-9]+]]:fpr64 = MLAv8i8 [[COPY2]], [[COPY1]], [[COPY]] 1763 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i8_]] 1764 %4:fpr(<8 x s8>) = COPY $d2 1765 %3:fpr(<8 x s8>) = COPY $d1 1766 %2:fpr(<8 x s8>) = COPY $d0 1767 %0:fpr(<8 x s8>) = G_MUL %3, %4 1768 %1:fpr(<8 x s8>) = G_ADD %2, %0 1769 $noreg = PATCHABLE_RET %1(<8 x s8>) 1770 1771... 1772--- 1773name: test_rule957_id928_at_idx62489 1774alignment: 2 1775legalized: true 1776regBankSelected: true 1777tracksRegLiveness: true 1778registers: 1779 - { id: 0, class: fpr } 1780 - { id: 1, class: fpr } 1781 - { id: 2, class: fpr } 1782 - { id: 3, class: fpr } 1783 - { id: 4, class: fpr } 1784liveins: 1785 - { reg: '$q0', virtual-reg: '%2' } 1786 - { reg: '$q1', virtual-reg: '%3' } 1787 - { reg: '$q2', virtual-reg: '%4' } 1788body: | 1789 bb.0.entry: 1790 liveins: $q0, $q1, $q2 1791 1792 ; CHECK-LABEL: name: test_rule957_id928_at_idx62489 1793 ; CHECK: liveins: $q0, $q1, $q2 1794 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1795 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1796 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1797 ; CHECK: [[MLAv16i8_:%[0-9]+]]:fpr128 = MLAv16i8 [[COPY2]], [[COPY1]], [[COPY]] 1798 ; CHECK: $noreg = PATCHABLE_RET [[MLAv16i8_]] 1799 %4:fpr(<16 x s8>) = COPY $q2 1800 %3:fpr(<16 x s8>) = COPY $q1 1801 %2:fpr(<16 x s8>) = COPY $q0 1802 %0:fpr(<16 x s8>) = G_MUL %3, %4 1803 %1:fpr(<16 x s8>) = G_ADD %2, %0 1804 $noreg = PATCHABLE_RET %1(<16 x s8>) 1805 1806... 1807--- 1808name: test_rule958_id929_at_idx62577 1809alignment: 2 1810legalized: true 1811regBankSelected: true 1812tracksRegLiveness: true 1813registers: 1814 - { id: 0, class: fpr } 1815 - { id: 1, class: fpr } 1816 - { id: 2, class: fpr } 1817 - { id: 3, class: fpr } 1818 - { id: 4, class: fpr } 1819liveins: 1820 - { reg: '$d0', virtual-reg: '%2' } 1821 - { reg: '$d1', virtual-reg: '%3' } 1822 - { reg: '$d2', virtual-reg: '%4' } 1823body: | 1824 bb.0.entry: 1825 liveins: $d0, $d1, $d2 1826 1827 ; CHECK-LABEL: name: test_rule958_id929_at_idx62577 1828 ; CHECK: liveins: $d0, $d1, $d2 1829 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 1830 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1831 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 1832 ; CHECK: [[MLAv4i16_:%[0-9]+]]:fpr64 = MLAv4i16 [[COPY2]], [[COPY1]], [[COPY]] 1833 ; CHECK: $noreg = PATCHABLE_RET [[MLAv4i16_]] 1834 %4:fpr(<4 x s16>) = COPY $d2 1835 %3:fpr(<4 x s16>) = COPY $d1 1836 %2:fpr(<4 x s16>) = COPY $d0 1837 %0:fpr(<4 x s16>) = G_MUL %3, %4 1838 %1:fpr(<4 x s16>) = G_ADD %2, %0 1839 $noreg = PATCHABLE_RET %1(<4 x s16>) 1840 1841... 1842--- 1843name: test_rule959_id930_at_idx62665 1844alignment: 2 1845legalized: true 1846regBankSelected: true 1847tracksRegLiveness: true 1848registers: 1849 - { id: 0, class: fpr } 1850 - { id: 1, class: fpr } 1851 - { id: 2, class: fpr } 1852 - { id: 3, class: fpr } 1853 - { id: 4, class: fpr } 1854liveins: 1855 - { reg: '$q0', virtual-reg: '%2' } 1856 - { reg: '$q1', virtual-reg: '%3' } 1857 - { reg: '$q2', virtual-reg: '%4' } 1858body: | 1859 bb.0.entry: 1860 liveins: $q0, $q1, $q2 1861 1862 ; CHECK-LABEL: name: test_rule959_id930_at_idx62665 1863 ; CHECK: liveins: $q0, $q1, $q2 1864 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 1865 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1866 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 1867 ; CHECK: [[MLAv8i16_:%[0-9]+]]:fpr128 = MLAv8i16 [[COPY2]], [[COPY1]], [[COPY]] 1868 ; CHECK: $noreg = PATCHABLE_RET [[MLAv8i16_]] 1869 %4:fpr(<8 x s16>) = COPY $q2 1870 %3:fpr(<8 x s16>) = COPY $q1 1871 %2:fpr(<8 x s16>) = COPY $q0 1872 %0:fpr(<8 x s16>) = G_MUL %3, %4 1873 %1:fpr(<8 x s16>) = G_ADD %2, %0 1874 $noreg = PATCHABLE_RET %1(<8 x s16>) 1875 1876... 1877--- 1878name: test_rule962_id1272_at_idx62929 1879alignment: 2 1880legalized: true 1881regBankSelected: true 1882tracksRegLiveness: true 1883registers: 1884 - { id: 0, class: fpr } 1885 - { id: 1, class: fpr } 1886 - { id: 2, class: fpr } 1887 - { id: 3, class: fpr } 1888liveins: 1889 - { reg: '$q0', virtual-reg: '%2' } 1890 - { reg: '$d0', virtual-reg: '%3' } 1891body: | 1892 bb.0.entry: 1893 liveins: $q0, $d0 1894 1895 ; CHECK-LABEL: name: test_rule962_id1272_at_idx62929 1896 ; CHECK: liveins: $q0, $d0 1897 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1898 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1899 ; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1900 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]] 1901 %3:fpr(<8 x s8>) = COPY $d0 1902 %2:fpr(<8 x s16>) = COPY $q0 1903 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 1904 %1:fpr(<8 x s16>) = G_ADD %2, %0 1905 $noreg = PATCHABLE_RET %1(<8 x s16>) 1906 1907... 1908--- 1909name: test_rule963_id1274_at_idx63005 1910alignment: 2 1911legalized: true 1912regBankSelected: true 1913tracksRegLiveness: true 1914registers: 1915 - { id: 0, class: fpr } 1916 - { id: 1, class: fpr } 1917 - { id: 2, class: fpr } 1918 - { id: 3, class: fpr } 1919liveins: 1920 - { reg: '$q0', virtual-reg: '%2' } 1921 - { reg: '$d0', virtual-reg: '%3' } 1922body: | 1923 bb.0.entry: 1924 liveins: $q0, $d0 1925 1926 ; CHECK-LABEL: name: test_rule963_id1274_at_idx63005 1927 ; CHECK: liveins: $q0, $d0 1928 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1929 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1930 ; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]] 1931 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]] 1932 %3:fpr(<4 x s16>) = COPY $d0 1933 %2:fpr(<4 x s32>) = COPY $q0 1934 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 1935 %1:fpr(<4 x s32>) = G_ADD %2, %0 1936 $noreg = PATCHABLE_RET %1(<4 x s32>) 1937 1938... 1939--- 1940name: test_rule964_id1276_at_idx63081 1941alignment: 2 1942legalized: true 1943regBankSelected: true 1944tracksRegLiveness: true 1945registers: 1946 - { id: 0, class: fpr } 1947 - { id: 1, class: fpr } 1948 - { id: 2, class: fpr } 1949 - { id: 3, class: fpr } 1950liveins: 1951 - { reg: '$q0', virtual-reg: '%2' } 1952 - { reg: '$d0', virtual-reg: '%3' } 1953body: | 1954 bb.0.entry: 1955 liveins: $q0, $d0 1956 1957 ; CHECK-LABEL: name: test_rule964_id1276_at_idx63081 1958 ; CHECK: liveins: $q0, $d0 1959 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1960 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1961 ; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]] 1962 ; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]] 1963 %3:fpr(<2 x s32>) = COPY $d0 1964 %2:fpr(<2 x s64>) = COPY $q0 1965 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 1966 %1:fpr(<2 x s64>) = G_ADD %2, %0 1967 $noreg = PATCHABLE_RET %1(<2 x s64>) 1968 1969... 1970--- 1971name: test_rule965_id1332_at_idx63157 1972alignment: 2 1973legalized: true 1974regBankSelected: true 1975tracksRegLiveness: true 1976registers: 1977 - { id: 0, class: fpr } 1978 - { id: 1, class: fpr } 1979 - { id: 2, class: fpr } 1980 - { id: 3, class: fpr } 1981liveins: 1982 - { reg: '$q0', virtual-reg: '%2' } 1983 - { reg: '$d0', virtual-reg: '%3' } 1984body: | 1985 bb.0.entry: 1986 liveins: $q0, $d0 1987 1988 ; CHECK-LABEL: name: test_rule965_id1332_at_idx63157 1989 ; CHECK: liveins: $q0, $d0 1990 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1991 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 1992 ; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]] 1993 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]] 1994 %3:fpr(<8 x s8>) = COPY $d0 1995 %2:fpr(<8 x s16>) = COPY $q0 1996 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 1997 %1:fpr(<8 x s16>) = G_ADD %2, %0 1998 $noreg = PATCHABLE_RET %1(<8 x s16>) 1999 2000... 2001--- 2002name: test_rule966_id1334_at_idx63233 2003alignment: 2 2004legalized: true 2005regBankSelected: true 2006tracksRegLiveness: true 2007registers: 2008 - { id: 0, class: fpr } 2009 - { id: 1, class: fpr } 2010 - { id: 2, class: fpr } 2011 - { id: 3, class: fpr } 2012liveins: 2013 - { reg: '$q0', virtual-reg: '%2' } 2014 - { reg: '$d0', virtual-reg: '%3' } 2015body: | 2016 bb.0.entry: 2017 liveins: $q0, $d0 2018 2019 ; CHECK-LABEL: name: test_rule966_id1334_at_idx63233 2020 ; CHECK: liveins: $q0, $d0 2021 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2022 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2023 ; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]] 2024 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]] 2025 %3:fpr(<4 x s16>) = COPY $d0 2026 %2:fpr(<4 x s32>) = COPY $q0 2027 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 2028 %1:fpr(<4 x s32>) = G_ADD %2, %0 2029 $noreg = PATCHABLE_RET %1(<4 x s32>) 2030 2031... 2032--- 2033name: test_rule967_id1336_at_idx63309 2034alignment: 2 2035legalized: true 2036regBankSelected: true 2037tracksRegLiveness: true 2038registers: 2039 - { id: 0, class: fpr } 2040 - { id: 1, class: fpr } 2041 - { id: 2, class: fpr } 2042 - { id: 3, class: fpr } 2043liveins: 2044 - { reg: '$q0', virtual-reg: '%2' } 2045 - { reg: '$d0', virtual-reg: '%3' } 2046body: | 2047 bb.0.entry: 2048 liveins: $q0, $d0 2049 2050 ; CHECK-LABEL: name: test_rule967_id1336_at_idx63309 2051 ; CHECK: liveins: $q0, $d0 2052 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2053 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2054 ; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]] 2055 ; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]] 2056 %3:fpr(<2 x s32>) = COPY $d0 2057 %2:fpr(<2 x s64>) = COPY $q0 2058 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 2059 %1:fpr(<2 x s64>) = G_ADD %2, %0 2060 $noreg = PATCHABLE_RET %1(<2 x s64>) 2061 2062... 2063--- 2064name: test_rule977_id933_at_idx64051 2065alignment: 2 2066legalized: true 2067regBankSelected: true 2068tracksRegLiveness: true 2069registers: 2070 - { id: 0, class: fpr } 2071 - { id: 1, class: fpr } 2072 - { id: 2, class: fpr } 2073 - { id: 3, class: fpr } 2074 - { id: 4, class: fpr } 2075liveins: 2076 - { reg: '$d0', virtual-reg: '%2' } 2077 - { reg: '$d1', virtual-reg: '%3' } 2078 - { reg: '$d2', virtual-reg: '%4' } 2079body: | 2080 bb.0.entry: 2081 liveins: $d0, $d1, $d2 2082 2083 ; CHECK-LABEL: name: test_rule977_id933_at_idx64051 2084 ; CHECK: liveins: $d0, $d1, $d2 2085 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2086 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2087 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2088 ; CHECK: [[MLSv8i8_:%[0-9]+]]:fpr64 = MLSv8i8 [[COPY2]], [[COPY1]], [[COPY]] 2089 ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i8_]] 2090 %4:fpr(<8 x s8>) = COPY $d2 2091 %3:fpr(<8 x s8>) = COPY $d1 2092 %2:fpr(<8 x s8>) = COPY $d0 2093 %0:fpr(<8 x s8>) = G_MUL %3, %4 2094 %1:fpr(<8 x s8>) = G_SUB %2, %0 2095 $noreg = PATCHABLE_RET %1(<8 x s8>) 2096 2097... 2098--- 2099name: test_rule978_id934_at_idx64139 2100alignment: 2 2101legalized: true 2102regBankSelected: true 2103tracksRegLiveness: true 2104registers: 2105 - { id: 0, class: fpr } 2106 - { id: 1, class: fpr } 2107 - { id: 2, class: fpr } 2108 - { id: 3, class: fpr } 2109 - { id: 4, class: fpr } 2110liveins: 2111 - { reg: '$q0', virtual-reg: '%2' } 2112 - { reg: '$q1', virtual-reg: '%3' } 2113 - { reg: '$q2', virtual-reg: '%4' } 2114body: | 2115 bb.0.entry: 2116 liveins: $q0, $q1, $q2 2117 2118 ; CHECK-LABEL: name: test_rule978_id934_at_idx64139 2119 ; CHECK: liveins: $q0, $q1, $q2 2120 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2121 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2122 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2123 ; CHECK: [[MLSv16i8_:%[0-9]+]]:fpr128 = MLSv16i8 [[COPY2]], [[COPY1]], [[COPY]] 2124 ; CHECK: $noreg = PATCHABLE_RET [[MLSv16i8_]] 2125 %4:fpr(<16 x s8>) = COPY $q2 2126 %3:fpr(<16 x s8>) = COPY $q1 2127 %2:fpr(<16 x s8>) = COPY $q0 2128 %0:fpr(<16 x s8>) = G_MUL %3, %4 2129 %1:fpr(<16 x s8>) = G_SUB %2, %0 2130 $noreg = PATCHABLE_RET %1(<16 x s8>) 2131 2132... 2133--- 2134name: test_rule979_id935_at_idx64227 2135alignment: 2 2136legalized: true 2137regBankSelected: true 2138tracksRegLiveness: true 2139registers: 2140 - { id: 0, class: fpr } 2141 - { id: 1, class: fpr } 2142 - { id: 2, class: fpr } 2143 - { id: 3, class: fpr } 2144 - { id: 4, class: fpr } 2145liveins: 2146 - { reg: '$d0', virtual-reg: '%2' } 2147 - { reg: '$d1', virtual-reg: '%3' } 2148 - { reg: '$d2', virtual-reg: '%4' } 2149body: | 2150 bb.0.entry: 2151 liveins: $d0, $d1, $d2 2152 2153 ; CHECK-LABEL: name: test_rule979_id935_at_idx64227 2154 ; CHECK: liveins: $d0, $d1, $d2 2155 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2156 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2157 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2158 ; CHECK: [[MLSv4i16_:%[0-9]+]]:fpr64 = MLSv4i16 [[COPY2]], [[COPY1]], [[COPY]] 2159 ; CHECK: $noreg = PATCHABLE_RET [[MLSv4i16_]] 2160 %4:fpr(<4 x s16>) = COPY $d2 2161 %3:fpr(<4 x s16>) = COPY $d1 2162 %2:fpr(<4 x s16>) = COPY $d0 2163 %0:fpr(<4 x s16>) = G_MUL %3, %4 2164 %1:fpr(<4 x s16>) = G_SUB %2, %0 2165 $noreg = PATCHABLE_RET %1(<4 x s16>) 2166 2167... 2168--- 2169name: test_rule980_id936_at_idx64315 2170alignment: 2 2171legalized: true 2172regBankSelected: true 2173tracksRegLiveness: true 2174registers: 2175 - { id: 0, class: fpr } 2176 - { id: 1, class: fpr } 2177 - { id: 2, class: fpr } 2178 - { id: 3, class: fpr } 2179 - { id: 4, class: fpr } 2180liveins: 2181 - { reg: '$q0', virtual-reg: '%2' } 2182 - { reg: '$q1', virtual-reg: '%3' } 2183 - { reg: '$q2', virtual-reg: '%4' } 2184body: | 2185 bb.0.entry: 2186 liveins: $q0, $q1, $q2 2187 2188 ; CHECK-LABEL: name: test_rule980_id936_at_idx64315 2189 ; CHECK: liveins: $q0, $q1, $q2 2190 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2191 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2192 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2193 ; CHECK: [[MLSv8i16_:%[0-9]+]]:fpr128 = MLSv8i16 [[COPY2]], [[COPY1]], [[COPY]] 2194 ; CHECK: $noreg = PATCHABLE_RET [[MLSv8i16_]] 2195 %4:fpr(<8 x s16>) = COPY $q2 2196 %3:fpr(<8 x s16>) = COPY $q1 2197 %2:fpr(<8 x s16>) = COPY $q0 2198 %0:fpr(<8 x s16>) = G_MUL %3, %4 2199 %1:fpr(<8 x s16>) = G_SUB %2, %0 2200 $noreg = PATCHABLE_RET %1(<8 x s16>) 2201 2202... 2203--- 2204name: test_rule983_id1314_at_idx64579 2205alignment: 2 2206legalized: true 2207regBankSelected: true 2208tracksRegLiveness: true 2209registers: 2210 - { id: 0, class: fpr } 2211 - { id: 1, class: fpr } 2212 - { id: 2, class: fpr } 2213 - { id: 3, class: fpr } 2214liveins: 2215 - { reg: '$q0', virtual-reg: '%2' } 2216 - { reg: '$d0', virtual-reg: '%3' } 2217body: | 2218 bb.0.entry: 2219 liveins: $q0, $d0 2220 2221 ; CHECK-LABEL: name: test_rule983_id1314_at_idx64579 2222 ; CHECK: liveins: $q0, $d0 2223 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2224 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2225 ; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]] 2226 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]] 2227 %3:fpr(<8 x s8>) = COPY $d0 2228 %2:fpr(<8 x s16>) = COPY $q0 2229 %0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>) 2230 %1:fpr(<8 x s16>) = G_SUB %2, %0 2231 $noreg = PATCHABLE_RET %1(<8 x s16>) 2232 2233... 2234--- 2235name: test_rule984_id1316_at_idx64655 2236alignment: 2 2237legalized: true 2238regBankSelected: true 2239tracksRegLiveness: true 2240registers: 2241 - { id: 0, class: fpr } 2242 - { id: 1, class: fpr } 2243 - { id: 2, class: fpr } 2244 - { id: 3, class: fpr } 2245liveins: 2246 - { reg: '$q0', virtual-reg: '%2' } 2247 - { reg: '$d0', virtual-reg: '%3' } 2248body: | 2249 bb.0.entry: 2250 liveins: $q0, $d0 2251 2252 ; CHECK-LABEL: name: test_rule984_id1316_at_idx64655 2253 ; CHECK: liveins: $q0, $d0 2254 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2255 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2256 ; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]] 2257 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]] 2258 %3:fpr(<4 x s16>) = COPY $d0 2259 %2:fpr(<4 x s32>) = COPY $q0 2260 %0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>) 2261 %1:fpr(<4 x s32>) = G_SUB %2, %0 2262 $noreg = PATCHABLE_RET %1(<4 x s32>) 2263 2264... 2265--- 2266name: test_rule985_id1318_at_idx64731 2267alignment: 2 2268legalized: true 2269regBankSelected: true 2270tracksRegLiveness: true 2271registers: 2272 - { id: 0, class: fpr } 2273 - { id: 1, class: fpr } 2274 - { id: 2, class: fpr } 2275 - { id: 3, class: fpr } 2276liveins: 2277 - { reg: '$q0', virtual-reg: '%2' } 2278 - { reg: '$d0', virtual-reg: '%3' } 2279body: | 2280 bb.0.entry: 2281 liveins: $q0, $d0 2282 2283 ; CHECK-LABEL: name: test_rule985_id1318_at_idx64731 2284 ; CHECK: liveins: $q0, $d0 2285 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2286 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2287 ; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]] 2288 ; CHECK: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]] 2289 %3:fpr(<2 x s32>) = COPY $d0 2290 %2:fpr(<2 x s64>) = COPY $q0 2291 %0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>) 2292 %1:fpr(<2 x s64>) = G_SUB %2, %0 2293 $noreg = PATCHABLE_RET %1(<2 x s64>) 2294 2295... 2296--- 2297name: test_rule986_id1362_at_idx64807 2298alignment: 2 2299legalized: true 2300regBankSelected: true 2301tracksRegLiveness: true 2302registers: 2303 - { id: 0, class: fpr } 2304 - { id: 1, class: fpr } 2305 - { id: 2, class: fpr } 2306 - { id: 3, class: fpr } 2307liveins: 2308 - { reg: '$q0', virtual-reg: '%2' } 2309 - { reg: '$d0', virtual-reg: '%3' } 2310body: | 2311 bb.0.entry: 2312 liveins: $q0, $d0 2313 2314 ; CHECK-LABEL: name: test_rule986_id1362_at_idx64807 2315 ; CHECK: liveins: $q0, $d0 2316 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2317 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2318 ; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]] 2319 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]] 2320 %3:fpr(<8 x s8>) = COPY $d0 2321 %2:fpr(<8 x s16>) = COPY $q0 2322 %0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>) 2323 %1:fpr(<8 x s16>) = G_SUB %2, %0 2324 $noreg = PATCHABLE_RET %1(<8 x s16>) 2325 2326... 2327--- 2328name: test_rule987_id1364_at_idx64883 2329alignment: 2 2330legalized: true 2331regBankSelected: true 2332tracksRegLiveness: true 2333registers: 2334 - { id: 0, class: fpr } 2335 - { id: 1, class: fpr } 2336 - { id: 2, class: fpr } 2337 - { id: 3, class: fpr } 2338liveins: 2339 - { reg: '$q0', virtual-reg: '%2' } 2340 - { reg: '$d0', virtual-reg: '%3' } 2341body: | 2342 bb.0.entry: 2343 liveins: $q0, $d0 2344 2345 ; CHECK-LABEL: name: test_rule987_id1364_at_idx64883 2346 ; CHECK: liveins: $q0, $d0 2347 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2348 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2349 ; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]] 2350 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]] 2351 %3:fpr(<4 x s16>) = COPY $d0 2352 %2:fpr(<4 x s32>) = COPY $q0 2353 %0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>) 2354 %1:fpr(<4 x s32>) = G_SUB %2, %0 2355 $noreg = PATCHABLE_RET %1(<4 x s32>) 2356 2357... 2358--- 2359name: test_rule988_id1366_at_idx64959 2360alignment: 2 2361legalized: true 2362regBankSelected: true 2363tracksRegLiveness: true 2364registers: 2365 - { id: 0, class: fpr } 2366 - { id: 1, class: fpr } 2367 - { id: 2, class: fpr } 2368 - { id: 3, class: fpr } 2369liveins: 2370 - { reg: '$q0', virtual-reg: '%2' } 2371 - { reg: '$d0', virtual-reg: '%3' } 2372body: | 2373 bb.0.entry: 2374 liveins: $q0, $d0 2375 2376 ; CHECK-LABEL: name: test_rule988_id1366_at_idx64959 2377 ; CHECK: liveins: $q0, $d0 2378 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 2379 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2380 ; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]] 2381 ; CHECK: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]] 2382 %3:fpr(<2 x s32>) = COPY $d0 2383 %2:fpr(<2 x s64>) = COPY $q0 2384 %0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>) 2385 %1:fpr(<2 x s64>) = G_SUB %2, %0 2386 $noreg = PATCHABLE_RET %1(<2 x s64>) 2387 2388... 2389--- 2390name: test_rule990_id432_at_idx65123 2391alignment: 2 2392legalized: true 2393regBankSelected: true 2394tracksRegLiveness: true 2395registers: 2396 - { id: 0, class: fpr } 2397 - { id: 1, class: fpr } 2398 - { id: 2, class: fpr } 2399 - { id: 3, class: fpr } 2400 - { id: 4, class: fpr } 2401liveins: 2402 - { reg: '$s0', virtual-reg: '%2' } 2403 - { reg: '$s1', virtual-reg: '%3' } 2404 - { reg: '$s2', virtual-reg: '%4' } 2405body: | 2406 bb.0.entry: 2407 liveins: $s0, $s1, $s2 2408 2409 ; CHECK-LABEL: name: test_rule990_id432_at_idx65123 2410 ; CHECK: liveins: $s0, $s1, $s2 2411 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2 2412 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 2413 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0 2414 ; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]] 2415 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]] 2416 %4:fpr(s32) = COPY $s2 2417 %3:fpr(s32) = COPY $s1 2418 %2:fpr(s32) = COPY $s0 2419 %0:fpr(s32) = G_FMA %2, %3, %4 2420 %1:fpr(s32) = G_FNEG %0 2421 $noreg = PATCHABLE_RET %1(s32) 2422 2423... 2424--- 2425name: test_rule991_id433_at_idx65211 2426alignment: 2 2427legalized: true 2428regBankSelected: true 2429tracksRegLiveness: true 2430registers: 2431 - { id: 0, class: fpr } 2432 - { id: 1, class: fpr } 2433 - { id: 2, class: fpr } 2434 - { id: 3, class: fpr } 2435 - { id: 4, class: fpr } 2436liveins: 2437 - { reg: '$d0', virtual-reg: '%2' } 2438 - { reg: '$d1', virtual-reg: '%3' } 2439 - { reg: '$d2', virtual-reg: '%4' } 2440body: | 2441 bb.0.entry: 2442 liveins: $d0, $d1, $d2 2443 2444 ; CHECK-LABEL: name: test_rule991_id433_at_idx65211 2445 ; CHECK: liveins: $d0, $d1, $d2 2446 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2447 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2448 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2449 ; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]] 2450 ; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]] 2451 %4:fpr(s64) = COPY $d2 2452 %3:fpr(s64) = COPY $d1 2453 %2:fpr(s64) = COPY $d0 2454 %0:fpr(s64) = G_FMA %2, %3, %4 2455 %1:fpr(s64) = G_FNEG %0 2456 $noreg = PATCHABLE_RET %1(s64) 2457 2458... 2459--- 2460name: test_rule993_id420_at_idx65375 2461alignment: 2 2462legalized: true 2463regBankSelected: true 2464tracksRegLiveness: true 2465registers: 2466 - { id: 0, class: fpr } 2467 - { id: 1, class: fpr } 2468 - { id: 2, class: fpr } 2469 - { id: 3, class: fpr } 2470liveins: 2471 - { reg: '$s0', virtual-reg: '%2' } 2472 - { reg: '$s1', virtual-reg: '%3' } 2473body: | 2474 bb.0.entry: 2475 liveins: $s0, $s1 2476 2477 ; CHECK-LABEL: name: test_rule993_id420_at_idx65375 2478 ; CHECK: liveins: $s0, $s1 2479 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1 2480 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0 2481 ; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = FNMULSrr [[COPY1]], [[COPY]] 2482 ; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]] 2483 %3:fpr(s32) = COPY $s1 2484 %2:fpr(s32) = COPY $s0 2485 %0:fpr(s32) = G_FMUL %2, %3 2486 %1:fpr(s32) = G_FNEG %0 2487 $noreg = PATCHABLE_RET %1(s32) 2488 2489... 2490--- 2491name: test_rule994_id421_at_idx65451 2492alignment: 2 2493legalized: true 2494regBankSelected: true 2495tracksRegLiveness: true 2496registers: 2497 - { id: 0, class: fpr } 2498 - { id: 1, class: fpr } 2499 - { id: 2, class: fpr } 2500 - { id: 3, class: fpr } 2501liveins: 2502 - { reg: '$d0', virtual-reg: '%2' } 2503 - { reg: '$d1', virtual-reg: '%3' } 2504body: | 2505 bb.0.entry: 2506 liveins: $d0, $d1 2507 2508 ; CHECK-LABEL: name: test_rule994_id421_at_idx65451 2509 ; CHECK: liveins: $d0, $d1 2510 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2511 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2512 ; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = FNMULDrr [[COPY1]], [[COPY]] 2513 ; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]] 2514 %3:fpr(s64) = COPY $d1 2515 %2:fpr(s64) = COPY $d0 2516 %0:fpr(s64) = G_FMUL %2, %3 2517 %1:fpr(s64) = G_FNEG %0 2518 $noreg = PATCHABLE_RET %1(s64) 2519 2520... 2521--- 2522name: test_rule1230_id2969_at_idx81784 2523alignment: 2 2524legalized: true 2525regBankSelected: true 2526tracksRegLiveness: true 2527registers: 2528 - { id: 0, class: gpr } 2529 - { id: 1, class: gpr } 2530liveins: 2531 - { reg: '$x0', virtual-reg: '%0' } 2532 - { reg: '$x1', virtual-reg: '%1' } 2533body: | 2534 bb.0.entry: 2535 liveins: $x0, $x1 2536 2537 ; CHECK-LABEL: name: test_rule1230_id2969_at_idx81784 2538 ; CHECK: liveins: $x0, $x1 2539 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 2540 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 2541 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] 2542 ; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store 8) 2543 ; CHECK: $noreg = PATCHABLE_RET 2544 %1:gpr(p0) = COPY $x1 2545 %0:gpr(<8 x s8>) = COPY $x0 2546 G_STORE %0(<8 x s8>), %1(p0) :: (store 8) 2547 $noreg = PATCHABLE_RET 2548 2549... 2550--- 2551name: test_rule1231_id2970_at_idx81816 2552alignment: 2 2553legalized: true 2554regBankSelected: true 2555tracksRegLiveness: true 2556registers: 2557 - { id: 0, class: gpr } 2558 - { id: 1, class: gpr } 2559liveins: 2560 - { reg: '$x0', virtual-reg: '%0' } 2561 - { reg: '$x1', virtual-reg: '%1' } 2562body: | 2563 bb.0.entry: 2564 liveins: $x0, $x1 2565 2566 ; CHECK-LABEL: name: test_rule1231_id2970_at_idx81816 2567 ; CHECK: liveins: $x0, $x1 2568 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1 2569 ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0 2570 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]] 2571 ; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store 8) 2572 ; CHECK: $noreg = PATCHABLE_RET 2573 %1:gpr(p0) = COPY $x1 2574 %0:gpr(<4 x s16>) = COPY $x0 2575 G_STORE %0(<4 x s16>), %1(p0) :: (store 8) 2576 $noreg = PATCHABLE_RET 2577 2578... 2579--- 2580name: test_rule1239_id894_at_idx82201 2581alignment: 2 2582legalized: true 2583regBankSelected: true 2584tracksRegLiveness: true 2585registers: 2586 - { id: 0, class: fpr } 2587 - { id: 1, class: fpr } 2588 - { id: 2, class: fpr } 2589 - { id: 3, class: fpr } 2590liveins: 2591 - { reg: '$d0', virtual-reg: '%1' } 2592 - { reg: '$d1', virtual-reg: '%2' } 2593 - { reg: '$d2', virtual-reg: '%3' } 2594body: | 2595 bb.0.entry: 2596 liveins: $d0, $d1, $d2 2597 2598 ; CHECK-LABEL: name: test_rule1239_id894_at_idx82201 2599 ; CHECK: liveins: $d0, $d1, $d2 2600 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2 2601 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 2602 ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0 2603 ; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]] 2604 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]] 2605 %3:fpr(<2 x s32>) = COPY $d2 2606 %2:fpr(<2 x s32>) = COPY $d1 2607 %1:fpr(<2 x s32>) = COPY $d0 2608 %0:fpr(<2 x s32>) = G_FMA %1, %2, %3 2609 $noreg = PATCHABLE_RET %0(<2 x s32>) 2610 2611... 2612--- 2613name: test_rule1240_id895_at_idx82269 2614alignment: 2 2615legalized: true 2616regBankSelected: true 2617tracksRegLiveness: true 2618registers: 2619 - { id: 0, class: fpr } 2620 - { id: 1, class: fpr } 2621 - { id: 2, class: fpr } 2622 - { id: 3, class: fpr } 2623liveins: 2624 - { reg: '$q0', virtual-reg: '%1' } 2625 - { reg: '$q1', virtual-reg: '%2' } 2626 - { reg: '$q2', virtual-reg: '%3' } 2627body: | 2628 bb.0.entry: 2629 liveins: $q0, $q1, $q2 2630 2631 ; CHECK-LABEL: name: test_rule1240_id895_at_idx82269 2632 ; CHECK: liveins: $q0, $q1, $q2 2633 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2634 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2635 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2636 ; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]] 2637 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]] 2638 %3:fpr(<4 x s32>) = COPY $q2 2639 %2:fpr(<4 x s32>) = COPY $q1 2640 %1:fpr(<4 x s32>) = COPY $q0 2641 %0:fpr(<4 x s32>) = G_FMA %1, %2, %3 2642 $noreg = PATCHABLE_RET %0(<4 x s32>) 2643 2644... 2645--- 2646name: test_rule1241_id896_at_idx82337 2647alignment: 2 2648legalized: true 2649regBankSelected: true 2650tracksRegLiveness: true 2651registers: 2652 - { id: 0, class: fpr } 2653 - { id: 1, class: fpr } 2654 - { id: 2, class: fpr } 2655 - { id: 3, class: fpr } 2656liveins: 2657 - { reg: '$q0', virtual-reg: '%1' } 2658 - { reg: '$q1', virtual-reg: '%2' } 2659 - { reg: '$q2', virtual-reg: '%3' } 2660body: | 2661 bb.0.entry: 2662 liveins: $q0, $q1, $q2 2663 2664 ; CHECK-LABEL: name: test_rule1241_id896_at_idx82337 2665 ; CHECK: liveins: $q0, $q1, $q2 2666 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2 2667 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 2668 ; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0 2669 ; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]] 2670 ; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]] 2671 %3:fpr(<2 x s64>) = COPY $q2 2672 %2:fpr(<2 x s64>) = COPY $q1 2673 %1:fpr(<2 x s64>) = COPY $q0 2674 %0:fpr(<2 x s64>) = G_FMA %1, %2, %3 2675 $noreg = PATCHABLE_RET %0(<2 x s64>) 2676 2677... 2678--- 2679name: test_rule1244_id751_at_idx82487 2680alignment: 2 2681legalized: true 2682regBankSelected: true 2683tracksRegLiveness: true 2684registers: 2685 - { id: 0, class: fpr } 2686 - { id: 1, class: fpr } 2687 - { id: 2, class: fpr } 2688liveins: 2689 - { reg: '$d0', virtual-reg: '%1' } 2690 - { reg: '$d1', virtual-reg: '%2' } 2691body: | 2692 bb.0.entry: 2693 liveins: $d0, $d1 2694 2695 ; CHECK-LABEL: name: test_rule1244_id751_at_idx82487 2696 ; CHECK: liveins: $d0, $d1 2697 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2698 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2699 ; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]] 2700 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]] 2701 %2:fpr(<8 x s8>) = COPY $d1 2702 %1:fpr(<8 x s8>) = COPY $d0 2703 %0:fpr(<8 x s8>) = G_ADD %1, %2 2704 $noreg = PATCHABLE_RET %0(<8 x s8>) 2705 2706... 2707--- 2708name: test_rule1245_id752_at_idx82530 2709alignment: 2 2710legalized: true 2711regBankSelected: true 2712tracksRegLiveness: true 2713registers: 2714 - { id: 0, class: fpr } 2715 - { id: 1, class: fpr } 2716 - { id: 2, class: fpr } 2717liveins: 2718 - { reg: '$q0', virtual-reg: '%1' } 2719 - { reg: '$q1', virtual-reg: '%2' } 2720body: | 2721 bb.0.entry: 2722 liveins: $q0, $q1 2723 2724 ; CHECK-LABEL: name: test_rule1245_id752_at_idx82530 2725 ; CHECK: liveins: $q0, $q1 2726 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2727 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2728 ; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]] 2729 ; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]] 2730 %2:fpr(<16 x s8>) = COPY $q1 2731 %1:fpr(<16 x s8>) = COPY $q0 2732 %0:fpr(<16 x s8>) = G_ADD %1, %2 2733 $noreg = PATCHABLE_RET %0(<16 x s8>) 2734 2735... 2736--- 2737name: test_rule1246_id753_at_idx82573 2738alignment: 2 2739legalized: true 2740regBankSelected: true 2741tracksRegLiveness: true 2742registers: 2743 - { id: 0, class: fpr } 2744 - { id: 1, class: fpr } 2745 - { id: 2, class: fpr } 2746liveins: 2747 - { reg: '$d0', virtual-reg: '%1' } 2748 - { reg: '$d1', virtual-reg: '%2' } 2749body: | 2750 bb.0.entry: 2751 liveins: $d0, $d1 2752 2753 ; CHECK-LABEL: name: test_rule1246_id753_at_idx82573 2754 ; CHECK: liveins: $d0, $d1 2755 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2756 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2757 ; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]] 2758 ; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]] 2759 %2:fpr(<4 x s16>) = COPY $d1 2760 %1:fpr(<4 x s16>) = COPY $d0 2761 %0:fpr(<4 x s16>) = G_ADD %1, %2 2762 $noreg = PATCHABLE_RET %0(<4 x s16>) 2763 2764... 2765--- 2766name: test_rule1247_id754_at_idx82616 2767alignment: 2 2768legalized: true 2769regBankSelected: true 2770tracksRegLiveness: true 2771registers: 2772 - { id: 0, class: fpr } 2773 - { id: 1, class: fpr } 2774 - { id: 2, class: fpr } 2775liveins: 2776 - { reg: '$q0', virtual-reg: '%1' } 2777 - { reg: '$q1', virtual-reg: '%2' } 2778body: | 2779 bb.0.entry: 2780 liveins: $q0, $q1 2781 2782 ; CHECK-LABEL: name: test_rule1247_id754_at_idx82616 2783 ; CHECK: liveins: $q0, $q1 2784 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2785 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2786 ; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]] 2787 ; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]] 2788 %2:fpr(<8 x s16>) = COPY $q1 2789 %1:fpr(<8 x s16>) = COPY $q0 2790 %0:fpr(<8 x s16>) = G_ADD %1, %2 2791 $noreg = PATCHABLE_RET %0(<8 x s16>) 2792 2793... 2794--- 2795name: test_rule1254_id1162_at_idx82913 2796alignment: 2 2797legalized: true 2798regBankSelected: true 2799tracksRegLiveness: true 2800registers: 2801 - { id: 0, class: fpr } 2802 - { id: 1, class: fpr } 2803 - { id: 2, class: fpr } 2804liveins: 2805 - { reg: '$d0', virtual-reg: '%1' } 2806 - { reg: '$d1', virtual-reg: '%2' } 2807body: | 2808 bb.0.entry: 2809 liveins: $d0, $d1 2810 2811 ; CHECK-LABEL: name: test_rule1254_id1162_at_idx82913 2812 ; CHECK: liveins: $d0, $d1 2813 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2814 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2815 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] 2816 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]] 2817 %2:fpr(<8 x s8>) = COPY $d1 2818 %1:fpr(<8 x s8>) = COPY $d0 2819 %0:fpr(<8 x s8>) = G_AND %1, %2 2820 $noreg = PATCHABLE_RET %0(<8 x s8>) 2821 2822... 2823--- 2824name: test_rule1255_id1163_at_idx82956 2825alignment: 2 2826legalized: true 2827regBankSelected: true 2828tracksRegLiveness: true 2829registers: 2830 - { id: 0, class: fpr } 2831 - { id: 1, class: fpr } 2832 - { id: 2, class: fpr } 2833liveins: 2834 - { reg: '$q0', virtual-reg: '%1' } 2835 - { reg: '$q1', virtual-reg: '%2' } 2836body: | 2837 bb.0.entry: 2838 liveins: $q0, $q1 2839 2840 ; CHECK-LABEL: name: test_rule1255_id1163_at_idx82956 2841 ; CHECK: liveins: $q0, $q1 2842 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2843 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2844 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] 2845 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]] 2846 %2:fpr(<16 x s8>) = COPY $q1 2847 %1:fpr(<16 x s8>) = COPY $q0 2848 %0:fpr(<16 x s8>) = G_AND %1, %2 2849 $noreg = PATCHABLE_RET %0(<16 x s8>) 2850 2851... 2852--- 2853name: test_rule1256_id1751_at_idx82999 2854alignment: 2 2855legalized: true 2856regBankSelected: true 2857tracksRegLiveness: true 2858registers: 2859 - { id: 0, class: fpr } 2860 - { id: 1, class: fpr } 2861 - { id: 2, class: fpr } 2862liveins: 2863 - { reg: '$d0', virtual-reg: '%1' } 2864 - { reg: '$d1', virtual-reg: '%2' } 2865body: | 2866 bb.0.entry: 2867 liveins: $d0, $d1 2868 2869 ; CHECK-LABEL: name: test_rule1256_id1751_at_idx82999 2870 ; CHECK: liveins: $d0, $d1 2871 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2872 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2873 ; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]] 2874 ; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]] 2875 %2:fpr(<4 x s16>) = COPY $d1 2876 %1:fpr(<4 x s16>) = COPY $d0 2877 %0:fpr(<4 x s16>) = G_AND %1, %2 2878 $noreg = PATCHABLE_RET %0(<4 x s16>) 2879 2880... 2881--- 2882name: test_rule1259_id1754_at_idx83128 2883alignment: 2 2884legalized: true 2885regBankSelected: true 2886tracksRegLiveness: true 2887registers: 2888 - { id: 0, class: fpr } 2889 - { id: 1, class: fpr } 2890 - { id: 2, class: fpr } 2891liveins: 2892 - { reg: '$q0', virtual-reg: '%1' } 2893 - { reg: '$q1', virtual-reg: '%2' } 2894body: | 2895 bb.0.entry: 2896 liveins: $q0, $q1 2897 2898 ; CHECK-LABEL: name: test_rule1259_id1754_at_idx83128 2899 ; CHECK: liveins: $q0, $q1 2900 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2901 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2902 ; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]] 2903 ; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]] 2904 %2:fpr(<8 x s16>) = COPY $q1 2905 %1:fpr(<8 x s16>) = COPY $q0 2906 %0:fpr(<8 x s16>) = G_AND %1, %2 2907 $noreg = PATCHABLE_RET %0(<8 x s16>) 2908 2909... 2910--- 2911name: test_rule1268_id829_at_idx83513 2912alignment: 2 2913legalized: true 2914regBankSelected: true 2915tracksRegLiveness: true 2916registers: 2917 - { id: 0, class: fpr } 2918 - { id: 1, class: fpr } 2919 - { id: 2, class: fpr } 2920liveins: 2921 - { reg: '$d0', virtual-reg: '%1' } 2922 - { reg: '$d1', virtual-reg: '%2' } 2923body: | 2924 bb.0.entry: 2925 liveins: $d0, $d1 2926 2927 ; CHECK-LABEL: name: test_rule1268_id829_at_idx83513 2928 ; CHECK: liveins: $d0, $d1 2929 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 2930 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 2931 ; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = FADDv2f32 [[COPY1]], [[COPY]] 2932 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]] 2933 %2:fpr(<2 x s32>) = COPY $d1 2934 %1:fpr(<2 x s32>) = COPY $d0 2935 %0:fpr(<2 x s32>) = G_FADD %1, %2 2936 $noreg = PATCHABLE_RET %0(<2 x s32>) 2937 2938... 2939--- 2940name: test_rule1269_id830_at_idx83556 2941alignment: 2 2942legalized: true 2943regBankSelected: true 2944tracksRegLiveness: true 2945registers: 2946 - { id: 0, class: fpr } 2947 - { id: 1, class: fpr } 2948 - { id: 2, class: fpr } 2949liveins: 2950 - { reg: '$q0', virtual-reg: '%1' } 2951 - { reg: '$q1', virtual-reg: '%2' } 2952body: | 2953 bb.0.entry: 2954 liveins: $q0, $q1 2955 2956 ; CHECK-LABEL: name: test_rule1269_id830_at_idx83556 2957 ; CHECK: liveins: $q0, $q1 2958 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2959 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2960 ; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = FADDv4f32 [[COPY1]], [[COPY]] 2961 ; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]] 2962 %2:fpr(<4 x s32>) = COPY $q1 2963 %1:fpr(<4 x s32>) = COPY $q0 2964 %0:fpr(<4 x s32>) = G_FADD %1, %2 2965 $noreg = PATCHABLE_RET %0(<4 x s32>) 2966 2967... 2968--- 2969name: test_rule1270_id831_at_idx83599 2970alignment: 2 2971legalized: true 2972regBankSelected: true 2973tracksRegLiveness: true 2974registers: 2975 - { id: 0, class: fpr } 2976 - { id: 1, class: fpr } 2977 - { id: 2, class: fpr } 2978liveins: 2979 - { reg: '$q0', virtual-reg: '%1' } 2980 - { reg: '$q1', virtual-reg: '%2' } 2981body: | 2982 bb.0.entry: 2983 liveins: $q0, $q1 2984 2985 ; CHECK-LABEL: name: test_rule1270_id831_at_idx83599 2986 ; CHECK: liveins: $q0, $q1 2987 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 2988 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 2989 ; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = FADDv2f64 [[COPY1]], [[COPY]] 2990 ; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]] 2991 %2:fpr(<2 x s64>) = COPY $q1 2992 %1:fpr(<2 x s64>) = COPY $q0 2993 %0:fpr(<2 x s64>) = G_FADD %1, %2 2994 $noreg = PATCHABLE_RET %0(<2 x s64>) 2995 2996... 2997--- 2998name: test_rule1276_id849_at_idx83857 2999alignment: 2 3000legalized: true 3001regBankSelected: true 3002tracksRegLiveness: true 3003registers: 3004 - { id: 0, class: fpr } 3005 - { id: 1, class: fpr } 3006 - { id: 2, class: fpr } 3007liveins: 3008 - { reg: '$d0', virtual-reg: '%1' } 3009 - { reg: '$d1', virtual-reg: '%2' } 3010body: | 3011 bb.0.entry: 3012 liveins: $d0, $d1 3013 3014 ; CHECK-LABEL: name: test_rule1276_id849_at_idx83857 3015 ; CHECK: liveins: $d0, $d1 3016 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3017 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3018 ; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = FDIVv2f32 [[COPY1]], [[COPY]] 3019 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]] 3020 %2:fpr(<2 x s32>) = COPY $d1 3021 %1:fpr(<2 x s32>) = COPY $d0 3022 %0:fpr(<2 x s32>) = G_FDIV %1, %2 3023 $noreg = PATCHABLE_RET %0(<2 x s32>) 3024 3025... 3026--- 3027name: test_rule1277_id850_at_idx83900 3028alignment: 2 3029legalized: true 3030regBankSelected: true 3031tracksRegLiveness: true 3032registers: 3033 - { id: 0, class: fpr } 3034 - { id: 1, class: fpr } 3035 - { id: 2, class: fpr } 3036liveins: 3037 - { reg: '$q0', virtual-reg: '%1' } 3038 - { reg: '$q1', virtual-reg: '%2' } 3039body: | 3040 bb.0.entry: 3041 liveins: $q0, $q1 3042 3043 ; CHECK-LABEL: name: test_rule1277_id850_at_idx83900 3044 ; CHECK: liveins: $q0, $q1 3045 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3046 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3047 ; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = FDIVv4f32 [[COPY1]], [[COPY]] 3048 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]] 3049 %2:fpr(<4 x s32>) = COPY $q1 3050 %1:fpr(<4 x s32>) = COPY $q0 3051 %0:fpr(<4 x s32>) = G_FDIV %1, %2 3052 $noreg = PATCHABLE_RET %0(<4 x s32>) 3053 3054... 3055--- 3056name: test_rule1278_id851_at_idx83943 3057alignment: 2 3058legalized: true 3059regBankSelected: true 3060tracksRegLiveness: true 3061registers: 3062 - { id: 0, class: fpr } 3063 - { id: 1, class: fpr } 3064 - { id: 2, class: fpr } 3065liveins: 3066 - { reg: '$q0', virtual-reg: '%1' } 3067 - { reg: '$q1', virtual-reg: '%2' } 3068body: | 3069 bb.0.entry: 3070 liveins: $q0, $q1 3071 3072 ; CHECK-LABEL: name: test_rule1278_id851_at_idx83943 3073 ; CHECK: liveins: $q0, $q1 3074 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3075 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3076 ; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = FDIVv2f64 [[COPY1]], [[COPY]] 3077 ; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]] 3078 %2:fpr(<2 x s64>) = COPY $q1 3079 %1:fpr(<2 x s64>) = COPY $q0 3080 %0:fpr(<2 x s64>) = G_FDIV %1, %2 3081 $noreg = PATCHABLE_RET %0(<2 x s64>) 3082 3083... 3084--- 3085name: test_rule1284_id909_at_idx84201 3086alignment: 2 3087legalized: true 3088regBankSelected: true 3089tracksRegLiveness: true 3090registers: 3091 - { id: 0, class: fpr } 3092 - { id: 1, class: fpr } 3093 - { id: 2, class: fpr } 3094liveins: 3095 - { reg: '$d0', virtual-reg: '%1' } 3096 - { reg: '$d1', virtual-reg: '%2' } 3097body: | 3098 bb.0.entry: 3099 liveins: $d0, $d1 3100 3101 ; CHECK-LABEL: name: test_rule1284_id909_at_idx84201 3102 ; CHECK: liveins: $d0, $d1 3103 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3104 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3105 ; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = FMULv2f32 [[COPY1]], [[COPY]] 3106 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]] 3107 %2:fpr(<2 x s32>) = COPY $d1 3108 %1:fpr(<2 x s32>) = COPY $d0 3109 %0:fpr(<2 x s32>) = G_FMUL %1, %2 3110 $noreg = PATCHABLE_RET %0(<2 x s32>) 3111 3112... 3113--- 3114name: test_rule1285_id910_at_idx84244 3115alignment: 2 3116legalized: true 3117regBankSelected: true 3118tracksRegLiveness: true 3119registers: 3120 - { id: 0, class: fpr } 3121 - { id: 1, class: fpr } 3122 - { id: 2, class: fpr } 3123liveins: 3124 - { reg: '$q0', virtual-reg: '%1' } 3125 - { reg: '$q1', virtual-reg: '%2' } 3126body: | 3127 bb.0.entry: 3128 liveins: $q0, $q1 3129 3130 ; CHECK-LABEL: name: test_rule1285_id910_at_idx84244 3131 ; CHECK: liveins: $q0, $q1 3132 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3133 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3134 ; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = FMULv4f32 [[COPY1]], [[COPY]] 3135 ; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]] 3136 %2:fpr(<4 x s32>) = COPY $q1 3137 %1:fpr(<4 x s32>) = COPY $q0 3138 %0:fpr(<4 x s32>) = G_FMUL %1, %2 3139 $noreg = PATCHABLE_RET %0(<4 x s32>) 3140 3141... 3142--- 3143name: test_rule1286_id911_at_idx84287 3144alignment: 2 3145legalized: true 3146regBankSelected: true 3147tracksRegLiveness: true 3148registers: 3149 - { id: 0, class: fpr } 3150 - { id: 1, class: fpr } 3151 - { id: 2, class: fpr } 3152liveins: 3153 - { reg: '$q0', virtual-reg: '%1' } 3154 - { reg: '$q1', virtual-reg: '%2' } 3155body: | 3156 bb.0.entry: 3157 liveins: $q0, $q1 3158 3159 ; CHECK-LABEL: name: test_rule1286_id911_at_idx84287 3160 ; CHECK: liveins: $q0, $q1 3161 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3162 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3163 ; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = FMULv2f64 [[COPY1]], [[COPY]] 3164 ; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]] 3165 %2:fpr(<2 x s64>) = COPY $q1 3166 %1:fpr(<2 x s64>) = COPY $q0 3167 %0:fpr(<2 x s64>) = G_FMUL %1, %2 3168 $noreg = PATCHABLE_RET %0(<2 x s64>) 3169 3170... 3171--- 3172name: test_rule1292_id924_at_idx84545 3173alignment: 2 3174legalized: true 3175regBankSelected: true 3176tracksRegLiveness: true 3177registers: 3178 - { id: 0, class: fpr } 3179 - { id: 1, class: fpr } 3180 - { id: 2, class: fpr } 3181liveins: 3182 - { reg: '$d0', virtual-reg: '%1' } 3183 - { reg: '$d1', virtual-reg: '%2' } 3184body: | 3185 bb.0.entry: 3186 liveins: $d0, $d1 3187 3188 ; CHECK-LABEL: name: test_rule1292_id924_at_idx84545 3189 ; CHECK: liveins: $d0, $d1 3190 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3191 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3192 ; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = FSUBv2f32 [[COPY1]], [[COPY]] 3193 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]] 3194 %2:fpr(<2 x s32>) = COPY $d1 3195 %1:fpr(<2 x s32>) = COPY $d0 3196 %0:fpr(<2 x s32>) = G_FSUB %1, %2 3197 $noreg = PATCHABLE_RET %0(<2 x s32>) 3198 3199... 3200--- 3201name: test_rule1293_id925_at_idx84588 3202alignment: 2 3203legalized: true 3204regBankSelected: true 3205tracksRegLiveness: true 3206registers: 3207 - { id: 0, class: fpr } 3208 - { id: 1, class: fpr } 3209 - { id: 2, class: fpr } 3210liveins: 3211 - { reg: '$q0', virtual-reg: '%1' } 3212 - { reg: '$q1', virtual-reg: '%2' } 3213body: | 3214 bb.0.entry: 3215 liveins: $q0, $q1 3216 3217 ; CHECK-LABEL: name: test_rule1293_id925_at_idx84588 3218 ; CHECK: liveins: $q0, $q1 3219 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3220 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3221 ; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = FSUBv4f32 [[COPY1]], [[COPY]] 3222 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]] 3223 %2:fpr(<4 x s32>) = COPY $q1 3224 %1:fpr(<4 x s32>) = COPY $q0 3225 %0:fpr(<4 x s32>) = G_FSUB %1, %2 3226 $noreg = PATCHABLE_RET %0(<4 x s32>) 3227 3228... 3229--- 3230name: test_rule1294_id926_at_idx84631 3231alignment: 2 3232legalized: true 3233regBankSelected: true 3234tracksRegLiveness: true 3235registers: 3236 - { id: 0, class: fpr } 3237 - { id: 1, class: fpr } 3238 - { id: 2, class: fpr } 3239liveins: 3240 - { reg: '$q0', virtual-reg: '%1' } 3241 - { reg: '$q1', virtual-reg: '%2' } 3242body: | 3243 bb.0.entry: 3244 liveins: $q0, $q1 3245 3246 ; CHECK-LABEL: name: test_rule1294_id926_at_idx84631 3247 ; CHECK: liveins: $q0, $q1 3248 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3249 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3250 ; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = FSUBv2f64 [[COPY1]], [[COPY]] 3251 ; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]] 3252 %2:fpr(<2 x s64>) = COPY $q1 3253 %1:fpr(<2 x s64>) = COPY $q0 3254 %0:fpr(<2 x s64>) = G_FSUB %1, %2 3255 $noreg = PATCHABLE_RET %0(<2 x s64>) 3256 3257... 3258--- 3259name: test_rule1296_id939_at_idx84715 3260alignment: 2 3261legalized: true 3262regBankSelected: true 3263tracksRegLiveness: true 3264registers: 3265 - { id: 0, class: fpr } 3266 - { id: 1, class: fpr } 3267 - { id: 2, class: fpr } 3268liveins: 3269 - { reg: '$d0', virtual-reg: '%1' } 3270 - { reg: '$d1', virtual-reg: '%2' } 3271body: | 3272 bb.0.entry: 3273 liveins: $d0, $d1 3274 3275 ; CHECK-LABEL: name: test_rule1296_id939_at_idx84715 3276 ; CHECK: liveins: $d0, $d1 3277 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3278 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3279 ; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]] 3280 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i8_]] 3281 %2:fpr(<8 x s8>) = COPY $d1 3282 %1:fpr(<8 x s8>) = COPY $d0 3283 %0:fpr(<8 x s8>) = G_MUL %1, %2 3284 $noreg = PATCHABLE_RET %0(<8 x s8>) 3285 3286... 3287--- 3288name: test_rule1297_id940_at_idx84758 3289alignment: 2 3290legalized: true 3291regBankSelected: true 3292tracksRegLiveness: true 3293registers: 3294 - { id: 0, class: fpr } 3295 - { id: 1, class: fpr } 3296 - { id: 2, class: fpr } 3297liveins: 3298 - { reg: '$q0', virtual-reg: '%1' } 3299 - { reg: '$q1', virtual-reg: '%2' } 3300body: | 3301 bb.0.entry: 3302 liveins: $q0, $q1 3303 3304 ; CHECK-LABEL: name: test_rule1297_id940_at_idx84758 3305 ; CHECK: liveins: $q0, $q1 3306 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3307 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3308 ; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]] 3309 ; CHECK: $noreg = PATCHABLE_RET [[MULv16i8_]] 3310 %2:fpr(<16 x s8>) = COPY $q1 3311 %1:fpr(<16 x s8>) = COPY $q0 3312 %0:fpr(<16 x s8>) = G_MUL %1, %2 3313 $noreg = PATCHABLE_RET %0(<16 x s8>) 3314 3315... 3316--- 3317name: test_rule1298_id941_at_idx84801 3318alignment: 2 3319legalized: true 3320regBankSelected: true 3321tracksRegLiveness: true 3322registers: 3323 - { id: 0, class: fpr } 3324 - { id: 1, class: fpr } 3325 - { id: 2, class: fpr } 3326liveins: 3327 - { reg: '$d0', virtual-reg: '%1' } 3328 - { reg: '$d1', virtual-reg: '%2' } 3329body: | 3330 bb.0.entry: 3331 liveins: $d0, $d1 3332 3333 ; CHECK-LABEL: name: test_rule1298_id941_at_idx84801 3334 ; CHECK: liveins: $d0, $d1 3335 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3336 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3337 ; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]] 3338 ; CHECK: $noreg = PATCHABLE_RET [[MULv4i16_]] 3339 %2:fpr(<4 x s16>) = COPY $d1 3340 %1:fpr(<4 x s16>) = COPY $d0 3341 %0:fpr(<4 x s16>) = G_MUL %1, %2 3342 $noreg = PATCHABLE_RET %0(<4 x s16>) 3343 3344... 3345--- 3346name: test_rule1299_id942_at_idx84844 3347alignment: 2 3348legalized: true 3349regBankSelected: true 3350tracksRegLiveness: true 3351registers: 3352 - { id: 0, class: fpr } 3353 - { id: 1, class: fpr } 3354 - { id: 2, class: fpr } 3355liveins: 3356 - { reg: '$q0', virtual-reg: '%1' } 3357 - { reg: '$q1', virtual-reg: '%2' } 3358body: | 3359 bb.0.entry: 3360 liveins: $q0, $q1 3361 3362 ; CHECK-LABEL: name: test_rule1299_id942_at_idx84844 3363 ; CHECK: liveins: $q0, $q1 3364 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3365 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3366 ; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]] 3367 ; CHECK: $noreg = PATCHABLE_RET [[MULv8i16_]] 3368 %2:fpr(<8 x s16>) = COPY $q1 3369 %1:fpr(<8 x s16>) = COPY $q0 3370 %0:fpr(<8 x s16>) = G_MUL %1, %2 3371 $noreg = PATCHABLE_RET %0(<8 x s16>) 3372 3373... 3374--- 3375name: test_rule1304_id1174_at_idx85055 3376alignment: 2 3377legalized: true 3378regBankSelected: true 3379tracksRegLiveness: true 3380registers: 3381 - { id: 0, class: fpr } 3382 - { id: 1, class: fpr } 3383 - { id: 2, class: fpr } 3384liveins: 3385 - { reg: '$d0', virtual-reg: '%1' } 3386 - { reg: '$d1', virtual-reg: '%2' } 3387body: | 3388 bb.0.entry: 3389 liveins: $d0, $d1 3390 3391 ; CHECK-LABEL: name: test_rule1304_id1174_at_idx85055 3392 ; CHECK: liveins: $d0, $d1 3393 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3394 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3395 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] 3396 ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]] 3397 %2:fpr(<8 x s8>) = COPY $d1 3398 %1:fpr(<8 x s8>) = COPY $d0 3399 %0:fpr(<8 x s8>) = G_OR %1, %2 3400 $noreg = PATCHABLE_RET %0(<8 x s8>) 3401 3402... 3403--- 3404name: test_rule1305_id1175_at_idx85098 3405alignment: 2 3406legalized: true 3407regBankSelected: true 3408tracksRegLiveness: true 3409registers: 3410 - { id: 0, class: fpr } 3411 - { id: 1, class: fpr } 3412 - { id: 2, class: fpr } 3413liveins: 3414 - { reg: '$q0', virtual-reg: '%1' } 3415 - { reg: '$q1', virtual-reg: '%2' } 3416body: | 3417 bb.0.entry: 3418 liveins: $q0, $q1 3419 3420 ; CHECK-LABEL: name: test_rule1305_id1175_at_idx85098 3421 ; CHECK: liveins: $q0, $q1 3422 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3423 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3424 ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] 3425 ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]] 3426 %2:fpr(<16 x s8>) = COPY $q1 3427 %1:fpr(<16 x s8>) = COPY $q0 3428 %0:fpr(<16 x s8>) = G_OR %1, %2 3429 $noreg = PATCHABLE_RET %0(<16 x s8>) 3430 3431... 3432--- 3433name: test_rule1306_id1827_at_idx85141 3434alignment: 2 3435legalized: true 3436regBankSelected: true 3437tracksRegLiveness: true 3438registers: 3439 - { id: 0, class: fpr } 3440 - { id: 1, class: fpr } 3441 - { id: 2, class: fpr } 3442liveins: 3443 - { reg: '$d0', virtual-reg: '%1' } 3444 - { reg: '$d1', virtual-reg: '%2' } 3445body: | 3446 bb.0.entry: 3447 liveins: $d0, $d1 3448 3449 ; CHECK-LABEL: name: test_rule1306_id1827_at_idx85141 3450 ; CHECK: liveins: $d0, $d1 3451 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3452 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3453 ; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]] 3454 ; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]] 3455 %2:fpr(<4 x s16>) = COPY $d1 3456 %1:fpr(<4 x s16>) = COPY $d0 3457 %0:fpr(<4 x s16>) = G_OR %1, %2 3458 $noreg = PATCHABLE_RET %0(<4 x s16>) 3459 3460... 3461--- 3462name: test_rule1309_id1830_at_idx85270 3463alignment: 2 3464legalized: true 3465regBankSelected: true 3466tracksRegLiveness: true 3467registers: 3468 - { id: 0, class: fpr } 3469 - { id: 1, class: fpr } 3470 - { id: 2, class: fpr } 3471liveins: 3472 - { reg: '$q0', virtual-reg: '%1' } 3473 - { reg: '$q1', virtual-reg: '%2' } 3474body: | 3475 bb.0.entry: 3476 liveins: $q0, $q1 3477 3478 ; CHECK-LABEL: name: test_rule1309_id1830_at_idx85270 3479 ; CHECK: liveins: $q0, $q1 3480 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3481 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3482 ; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]] 3483 ; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]] 3484 %2:fpr(<8 x s16>) = COPY $q1 3485 %1:fpr(<8 x s16>) = COPY $q0 3486 %0:fpr(<8 x s16>) = G_OR %1, %2 3487 $noreg = PATCHABLE_RET %0(<8 x s16>) 3488 3489... 3490--- 3491name: test_rule1315_id1051_at_idx85522 3492alignment: 2 3493legalized: true 3494regBankSelected: true 3495tracksRegLiveness: true 3496registers: 3497 - { id: 0, class: fpr } 3498 - { id: 1, class: fpr } 3499 - { id: 2, class: fpr } 3500liveins: 3501 - { reg: '$d0', virtual-reg: '%1' } 3502 - { reg: '$d1', virtual-reg: '%2' } 3503body: | 3504 bb.0.entry: 3505 liveins: $d0, $d1 3506 3507 ; CHECK-LABEL: name: test_rule1315_id1051_at_idx85522 3508 ; CHECK: liveins: $d0, $d1 3509 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3510 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3511 ; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]] 3512 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]] 3513 %2:fpr(<8 x s8>) = COPY $d1 3514 %1:fpr(<8 x s8>) = COPY $d0 3515 %0:fpr(<8 x s8>) = G_SUB %1, %2 3516 $noreg = PATCHABLE_RET %0(<8 x s8>) 3517 3518... 3519--- 3520name: test_rule1316_id1052_at_idx85565 3521alignment: 2 3522legalized: true 3523regBankSelected: true 3524tracksRegLiveness: true 3525registers: 3526 - { id: 0, class: fpr } 3527 - { id: 1, class: fpr } 3528 - { id: 2, class: fpr } 3529liveins: 3530 - { reg: '$q0', virtual-reg: '%1' } 3531 - { reg: '$q1', virtual-reg: '%2' } 3532body: | 3533 bb.0.entry: 3534 liveins: $q0, $q1 3535 3536 ; CHECK-LABEL: name: test_rule1316_id1052_at_idx85565 3537 ; CHECK: liveins: $q0, $q1 3538 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3539 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3540 ; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]] 3541 ; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]] 3542 %2:fpr(<16 x s8>) = COPY $q1 3543 %1:fpr(<16 x s8>) = COPY $q0 3544 %0:fpr(<16 x s8>) = G_SUB %1, %2 3545 $noreg = PATCHABLE_RET %0(<16 x s8>) 3546 3547... 3548--- 3549name: test_rule1317_id1053_at_idx85608 3550alignment: 2 3551legalized: true 3552regBankSelected: true 3553tracksRegLiveness: true 3554registers: 3555 - { id: 0, class: fpr } 3556 - { id: 1, class: fpr } 3557 - { id: 2, class: fpr } 3558liveins: 3559 - { reg: '$d0', virtual-reg: '%1' } 3560 - { reg: '$d1', virtual-reg: '%2' } 3561body: | 3562 bb.0.entry: 3563 liveins: $d0, $d1 3564 3565 ; CHECK-LABEL: name: test_rule1317_id1053_at_idx85608 3566 ; CHECK: liveins: $d0, $d1 3567 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3568 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3569 ; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]] 3570 ; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]] 3571 %2:fpr(<4 x s16>) = COPY $d1 3572 %1:fpr(<4 x s16>) = COPY $d0 3573 %0:fpr(<4 x s16>) = G_SUB %1, %2 3574 $noreg = PATCHABLE_RET %0(<4 x s16>) 3575 3576... 3577--- 3578name: test_rule1318_id1054_at_idx85651 3579alignment: 2 3580legalized: true 3581regBankSelected: true 3582tracksRegLiveness: true 3583registers: 3584 - { id: 0, class: fpr } 3585 - { id: 1, class: fpr } 3586 - { id: 2, class: fpr } 3587liveins: 3588 - { reg: '$q0', virtual-reg: '%1' } 3589 - { reg: '$q1', virtual-reg: '%2' } 3590body: | 3591 bb.0.entry: 3592 liveins: $q0, $q1 3593 3594 ; CHECK-LABEL: name: test_rule1318_id1054_at_idx85651 3595 ; CHECK: liveins: $q0, $q1 3596 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3597 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3598 ; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]] 3599 ; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]] 3600 %2:fpr(<8 x s16>) = COPY $q1 3601 %1:fpr(<8 x s16>) = COPY $q0 3602 %0:fpr(<8 x s16>) = G_SUB %1, %2 3603 $noreg = PATCHABLE_RET %0(<8 x s16>) 3604 3605... 3606--- 3607name: test_rule1329_id1170_at_idx86118 3608alignment: 2 3609legalized: true 3610regBankSelected: true 3611tracksRegLiveness: true 3612registers: 3613 - { id: 0, class: fpr } 3614 - { id: 1, class: fpr } 3615 - { id: 2, class: fpr } 3616liveins: 3617 - { reg: '$d0', virtual-reg: '%1' } 3618 - { reg: '$d1', virtual-reg: '%2' } 3619body: | 3620 bb.0.entry: 3621 liveins: $d0, $d1 3622 3623 ; CHECK-LABEL: name: test_rule1329_id1170_at_idx86118 3624 ; CHECK: liveins: $d0, $d1 3625 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3626 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3627 ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] 3628 ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]] 3629 %2:fpr(<8 x s8>) = COPY $d1 3630 %1:fpr(<8 x s8>) = COPY $d0 3631 %0:fpr(<8 x s8>) = G_XOR %1, %2 3632 $noreg = PATCHABLE_RET %0(<8 x s8>) 3633 3634... 3635--- 3636name: test_rule1330_id1171_at_idx86161 3637alignment: 2 3638legalized: true 3639regBankSelected: true 3640tracksRegLiveness: true 3641registers: 3642 - { id: 0, class: fpr } 3643 - { id: 1, class: fpr } 3644 - { id: 2, class: fpr } 3645liveins: 3646 - { reg: '$q0', virtual-reg: '%1' } 3647 - { reg: '$q1', virtual-reg: '%2' } 3648body: | 3649 bb.0.entry: 3650 liveins: $q0, $q1 3651 3652 ; CHECK-LABEL: name: test_rule1330_id1171_at_idx86161 3653 ; CHECK: liveins: $q0, $q1 3654 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3655 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3656 ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] 3657 ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]] 3658 %2:fpr(<16 x s8>) = COPY $q1 3659 %1:fpr(<16 x s8>) = COPY $q0 3660 %0:fpr(<16 x s8>) = G_XOR %1, %2 3661 $noreg = PATCHABLE_RET %0(<16 x s8>) 3662 3663... 3664--- 3665name: test_rule1331_id1791_at_idx86204 3666alignment: 2 3667legalized: true 3668regBankSelected: true 3669tracksRegLiveness: true 3670registers: 3671 - { id: 0, class: fpr } 3672 - { id: 1, class: fpr } 3673 - { id: 2, class: fpr } 3674liveins: 3675 - { reg: '$d0', virtual-reg: '%1' } 3676 - { reg: '$d1', virtual-reg: '%2' } 3677body: | 3678 bb.0.entry: 3679 liveins: $d0, $d1 3680 3681 ; CHECK-LABEL: name: test_rule1331_id1791_at_idx86204 3682 ; CHECK: liveins: $d0, $d1 3683 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1 3684 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 3685 ; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]] 3686 ; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]] 3687 %2:fpr(<4 x s16>) = COPY $d1 3688 %1:fpr(<4 x s16>) = COPY $d0 3689 %0:fpr(<4 x s16>) = G_XOR %1, %2 3690 $noreg = PATCHABLE_RET %0(<4 x s16>) 3691 3692... 3693--- 3694name: test_rule1334_id1794_at_idx86333 3695alignment: 2 3696legalized: true 3697regBankSelected: true 3698tracksRegLiveness: true 3699registers: 3700 - { id: 0, class: fpr } 3701 - { id: 1, class: fpr } 3702 - { id: 2, class: fpr } 3703liveins: 3704 - { reg: '$q0', virtual-reg: '%1' } 3705 - { reg: '$q1', virtual-reg: '%2' } 3706body: | 3707 bb.0.entry: 3708 liveins: $q0, $q1 3709 3710 ; CHECK-LABEL: name: test_rule1334_id1794_at_idx86333 3711 ; CHECK: liveins: $q0, $q1 3712 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1 3713 ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 3714 ; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]] 3715 ; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]] 3716 %2:fpr(<8 x s16>) = COPY $q1 3717 %1:fpr(<8 x s16>) = COPY $q0 3718 %0:fpr(<8 x s16>) = G_XOR %1, %2 3719 $noreg = PATCHABLE_RET %0(<8 x s16>) 3720 3721... 3722--- 3723name: test_rule1337_id2925_at_idx86462 3724alignment: 2 3725legalized: true 3726regBankSelected: true 3727tracksRegLiveness: true 3728registers: 3729 - { id: 0, class: fpr } 3730 - { id: 1, class: fpr } 3731liveins: 3732 - { reg: '$d0', virtual-reg: '%1' } 3733body: | 3734 bb.0.entry: 3735 liveins: $d0 3736 3737 ; CHECK-LABEL: name: test_rule1337_id2925_at_idx86462 3738 ; CHECK: liveins: $d0 3739 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3740 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 3741 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]] 3742 %1:fpr(<8 x s8>) = COPY $d0 3743 %0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>) 3744 $noreg = PATCHABLE_RET %0(<8 x s16>) 3745 3746... 3747--- 3748name: test_rule1338_id2928_at_idx86507 3749alignment: 2 3750legalized: true 3751regBankSelected: true 3752tracksRegLiveness: true 3753registers: 3754 - { id: 0, class: fpr } 3755 - { id: 1, class: fpr } 3756liveins: 3757 - { reg: '$d0', virtual-reg: '%1' } 3758body: | 3759 bb.0.entry: 3760 liveins: $d0 3761 3762 ; CHECK-LABEL: name: test_rule1338_id2928_at_idx86507 3763 ; CHECK: liveins: $d0 3764 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3765 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 3766 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]] 3767 %1:fpr(<4 x s16>) = COPY $d0 3768 %0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>) 3769 $noreg = PATCHABLE_RET %0(<4 x s32>) 3770 3771... 3772--- 3773name: test_rule1339_id2931_at_idx86552 3774alignment: 2 3775legalized: true 3776regBankSelected: true 3777tracksRegLiveness: true 3778registers: 3779 - { id: 0, class: fpr } 3780 - { id: 1, class: fpr } 3781liveins: 3782 - { reg: '$d0', virtual-reg: '%1' } 3783body: | 3784 bb.0.entry: 3785 liveins: $d0 3786 3787 ; CHECK-LABEL: name: test_rule1339_id2931_at_idx86552 3788 ; CHECK: liveins: $d0 3789 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3790 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 3791 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]] 3792 %1:fpr(<2 x s32>) = COPY $d0 3793 %0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>) 3794 $noreg = PATCHABLE_RET %0(<2 x s64>) 3795 3796... 3797--- 3798name: test_rule1582_id372_at_idx97075 3799alignment: 2 3800legalized: true 3801regBankSelected: true 3802tracksRegLiveness: true 3803registers: 3804 - { id: 0, class: fpr } 3805 - { id: 1, class: fpr } 3806liveins: 3807 - { reg: '$s0', virtual-reg: '%1' } 3808body: | 3809 bb.0.entry: 3810 liveins: $s0 3811 3812 ; CHECK-LABEL: name: test_rule1582_id372_at_idx97075 3813 ; CHECK: liveins: $s0 3814 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 3815 ; CHECK: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]] 3816 ; CHECK: $noreg = PATCHABLE_RET [[FNEGSr]] 3817 %1:fpr(s32) = COPY $s0 3818 %0:fpr(s32) = G_FNEG %1 3819 $noreg = PATCHABLE_RET %0(s32) 3820 3821... 3822--- 3823name: test_rule1583_id373_at_idx97110 3824alignment: 2 3825legalized: true 3826regBankSelected: true 3827tracksRegLiveness: true 3828registers: 3829 - { id: 0, class: fpr } 3830 - { id: 1, class: fpr } 3831liveins: 3832 - { reg: '$d0', virtual-reg: '%1' } 3833body: | 3834 bb.0.entry: 3835 liveins: $d0 3836 3837 ; CHECK-LABEL: name: test_rule1583_id373_at_idx97110 3838 ; CHECK: liveins: $d0 3839 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3840 ; CHECK: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]] 3841 ; CHECK: $noreg = PATCHABLE_RET [[FNEGDr]] 3842 %1:fpr(s64) = COPY $d0 3843 %0:fpr(s64) = G_FNEG %1 3844 $noreg = PATCHABLE_RET %0(s64) 3845 3846... 3847--- 3848name: test_rule1586_id597_at_idx97215 3849alignment: 2 3850legalized: true 3851regBankSelected: true 3852tracksRegLiveness: true 3853registers: 3854 - { id: 0, class: fpr } 3855 - { id: 1, class: fpr } 3856liveins: 3857 - { reg: '$d0', virtual-reg: '%1' } 3858body: | 3859 bb.0.entry: 3860 liveins: $d0 3861 3862 ; CHECK-LABEL: name: test_rule1586_id597_at_idx97215 3863 ; CHECK: liveins: $d0 3864 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3865 ; CHECK: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]] 3866 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f32_]] 3867 %1:fpr(<2 x s32>) = COPY $d0 3868 %0:fpr(<2 x s32>) = G_FNEG %1 3869 $noreg = PATCHABLE_RET %0(<2 x s32>) 3870 3871... 3872--- 3873name: test_rule1587_id598_at_idx97250 3874alignment: 2 3875legalized: true 3876regBankSelected: true 3877tracksRegLiveness: true 3878registers: 3879 - { id: 0, class: fpr } 3880 - { id: 1, class: fpr } 3881liveins: 3882 - { reg: '$q0', virtual-reg: '%1' } 3883body: | 3884 bb.0.entry: 3885 liveins: $q0 3886 3887 ; CHECK-LABEL: name: test_rule1587_id598_at_idx97250 3888 ; CHECK: liveins: $q0 3889 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3890 ; CHECK: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]] 3891 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv4f32_]] 3892 %1:fpr(<4 x s32>) = COPY $q0 3893 %0:fpr(<4 x s32>) = G_FNEG %1 3894 $noreg = PATCHABLE_RET %0(<4 x s32>) 3895 3896... 3897--- 3898name: test_rule1588_id599_at_idx97285 3899alignment: 2 3900legalized: true 3901regBankSelected: true 3902tracksRegLiveness: true 3903registers: 3904 - { id: 0, class: fpr } 3905 - { id: 1, class: fpr } 3906liveins: 3907 - { reg: '$q0', virtual-reg: '%1' } 3908body: | 3909 bb.0.entry: 3910 liveins: $q0 3911 3912 ; CHECK-LABEL: name: test_rule1588_id599_at_idx97285 3913 ; CHECK: liveins: $q0 3914 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 3915 ; CHECK: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]] 3916 ; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f64_]] 3917 %1:fpr(<2 x s64>) = COPY $q0 3918 %0:fpr(<2 x s64>) = G_FNEG %1 3919 $noreg = PATCHABLE_RET %0(<2 x s64>) 3920 3921... 3922--- 3923name: test_rule1592_id2383_at_idx97425 3924alignment: 2 3925legalized: true 3926regBankSelected: true 3927tracksRegLiveness: true 3928registers: 3929 - { id: 0, class: fpr } 3930 - { id: 1, class: fpr } 3931liveins: 3932 - { reg: '$d0', virtual-reg: '%1' } 3933body: | 3934 bb.0.entry: 3935 liveins: $d0 3936 3937 ; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425 3938 ; CHECK: liveins: $d0 3939 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3940 ; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = FCVTLv2i32 [[COPY]] 3941 ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]] 3942 %1:fpr(<2 x s32>) = COPY $d0 3943 %0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>) 3944 $noreg = PATCHABLE_RET %0(<2 x s64>) 3945 3946... 3947--- 3948name: test_rule1593_id2385_at_idx97458 3949alignment: 2 3950legalized: true 3951regBankSelected: true 3952tracksRegLiveness: true 3953registers: 3954 - { id: 0, class: fpr } 3955 - { id: 1, class: fpr } 3956liveins: 3957 - { reg: '$d0', virtual-reg: '%1' } 3958body: | 3959 bb.0.entry: 3960 liveins: $d0 3961 3962 ; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458 3963 ; CHECK: liveins: $d0 3964 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3965 ; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = FCVTLv4i16 [[COPY]] 3966 ; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]] 3967 %1:fpr(<4 x s16>) = COPY $d0 3968 %0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>) 3969 $noreg = PATCHABLE_RET %0(<4 x s32>) 3970 3971... 3972--- 3973name: test_rule1602_id587_at_idx97771 3974alignment: 2 3975legalized: true 3976regBankSelected: true 3977tracksRegLiveness: true 3978registers: 3979 - { id: 0, class: fpr } 3980 - { id: 1, class: fpr } 3981liveins: 3982 - { reg: '$d0', virtual-reg: '%1' } 3983body: | 3984 bb.0.entry: 3985 liveins: $d0 3986 3987 ; CHECK-LABEL: name: test_rule1602_id587_at_idx97771 3988 ; CHECK: liveins: $d0 3989 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 3990 ; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = FCVTZSv2f32 [[COPY]] 3991 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]] 3992 %1:fpr(<2 x s32>) = COPY $d0 3993 %0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>) 3994 $noreg = PATCHABLE_RET %0(<2 x s32>) 3995 3996... 3997--- 3998name: test_rule1603_id588_at_idx97806 3999alignment: 2 4000legalized: true 4001regBankSelected: true 4002tracksRegLiveness: true 4003registers: 4004 - { id: 0, class: fpr } 4005 - { id: 1, class: fpr } 4006liveins: 4007 - { reg: '$q0', virtual-reg: '%1' } 4008body: | 4009 bb.0.entry: 4010 liveins: $q0 4011 4012 ; CHECK-LABEL: name: test_rule1603_id588_at_idx97806 4013 ; CHECK: liveins: $q0 4014 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4015 ; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = FCVTZSv4f32 [[COPY]] 4016 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]] 4017 %1:fpr(<4 x s32>) = COPY $q0 4018 %0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>) 4019 $noreg = PATCHABLE_RET %0(<4 x s32>) 4020 4021... 4022--- 4023name: test_rule1604_id589_at_idx97841 4024alignment: 2 4025legalized: true 4026regBankSelected: true 4027tracksRegLiveness: true 4028registers: 4029 - { id: 0, class: fpr } 4030 - { id: 1, class: fpr } 4031liveins: 4032 - { reg: '$q0', virtual-reg: '%1' } 4033body: | 4034 bb.0.entry: 4035 liveins: $q0 4036 4037 ; CHECK-LABEL: name: test_rule1604_id589_at_idx97841 4038 ; CHECK: liveins: $q0 4039 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4040 ; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = FCVTZSv2f64 [[COPY]] 4041 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]] 4042 %1:fpr(<2 x s64>) = COPY $q0 4043 %0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>) 4044 $noreg = PATCHABLE_RET %0(<2 x s64>) 4045 4046... 4047--- 4048name: test_rule1613_id592_at_idx98156 4049alignment: 2 4050legalized: true 4051regBankSelected: true 4052tracksRegLiveness: true 4053registers: 4054 - { id: 0, class: fpr } 4055 - { id: 1, class: fpr } 4056liveins: 4057 - { reg: '$d0', virtual-reg: '%1' } 4058body: | 4059 bb.0.entry: 4060 liveins: $d0 4061 4062 ; CHECK-LABEL: name: test_rule1613_id592_at_idx98156 4063 ; CHECK: liveins: $d0 4064 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4065 ; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = FCVTZUv2f32 [[COPY]] 4066 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]] 4067 %1:fpr(<2 x s32>) = COPY $d0 4068 %0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>) 4069 $noreg = PATCHABLE_RET %0(<2 x s32>) 4070 4071... 4072--- 4073name: test_rule1614_id593_at_idx98191 4074alignment: 2 4075legalized: true 4076regBankSelected: true 4077tracksRegLiveness: true 4078registers: 4079 - { id: 0, class: fpr } 4080 - { id: 1, class: fpr } 4081liveins: 4082 - { reg: '$q0', virtual-reg: '%1' } 4083body: | 4084 bb.0.entry: 4085 liveins: $q0 4086 4087 ; CHECK-LABEL: name: test_rule1614_id593_at_idx98191 4088 ; CHECK: liveins: $q0 4089 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4090 ; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = FCVTZUv4f32 [[COPY]] 4091 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]] 4092 %1:fpr(<4 x s32>) = COPY $q0 4093 %0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>) 4094 $noreg = PATCHABLE_RET %0(<4 x s32>) 4095 4096... 4097--- 4098name: test_rule1615_id594_at_idx98226 4099alignment: 2 4100legalized: true 4101regBankSelected: true 4102tracksRegLiveness: true 4103registers: 4104 - { id: 0, class: fpr } 4105 - { id: 1, class: fpr } 4106liveins: 4107 - { reg: '$q0', virtual-reg: '%1' } 4108body: | 4109 bb.0.entry: 4110 liveins: $q0 4111 4112 ; CHECK-LABEL: name: test_rule1615_id594_at_idx98226 4113 ; CHECK: liveins: $q0 4114 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4115 ; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = FCVTZUv2f64 [[COPY]] 4116 ; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]] 4117 %1:fpr(<2 x s64>) = COPY $q0 4118 %0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>) 4119 $noreg = PATCHABLE_RET %0(<2 x s64>) 4120 4121... 4122--- 4123name: test_rule1619_id2389_at_idx98366 4124alignment: 2 4125legalized: true 4126regBankSelected: true 4127tracksRegLiveness: true 4128registers: 4129 - { id: 0, class: fpr } 4130 - { id: 1, class: fpr } 4131liveins: 4132 - { reg: '$q0', virtual-reg: '%1' } 4133body: | 4134 bb.0.entry: 4135 liveins: $q0 4136 4137 ; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366 4138 ; CHECK: liveins: $q0 4139 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4140 ; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = FCVTNv2i32 [[COPY]] 4141 ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]] 4142 %1:fpr(<2 x s64>) = COPY $q0 4143 %0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>) 4144 $noreg = PATCHABLE_RET %0(<2 x s32>) 4145 4146... 4147--- 4148name: test_rule1620_id2390_at_idx98399 4149alignment: 2 4150legalized: true 4151regBankSelected: true 4152tracksRegLiveness: true 4153registers: 4154 - { id: 0, class: fpr } 4155 - { id: 1, class: fpr } 4156liveins: 4157 - { reg: '$q0', virtual-reg: '%1' } 4158body: | 4159 bb.0.entry: 4160 liveins: $q0 4161 4162 ; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399 4163 ; CHECK: liveins: $q0 4164 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4165 ; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = FCVTNv4i16 [[COPY]] 4166 ; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]] 4167 %1:fpr(<4 x s32>) = COPY $q0 4168 %0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>) 4169 $noreg = PATCHABLE_RET %0(<4 x s16>) 4170 4171... 4172--- 4173name: test_rule1621_id2923_at_idx98432 4174alignment: 2 4175legalized: true 4176regBankSelected: true 4177tracksRegLiveness: true 4178registers: 4179 - { id: 0, class: fpr } 4180 - { id: 1, class: fpr } 4181liveins: 4182 - { reg: '$d0', virtual-reg: '%1' } 4183body: | 4184 bb.0.entry: 4185 liveins: $d0 4186 4187 ; CHECK-LABEL: name: test_rule1621_id2923_at_idx98432 4188 ; CHECK: liveins: $d0 4189 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4190 ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0 4191 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]] 4192 %1:fpr(<8 x s8>) = COPY $d0 4193 %0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>) 4194 $noreg = PATCHABLE_RET %0(<8 x s16>) 4195 4196... 4197--- 4198name: test_rule1622_id2926_at_idx98477 4199alignment: 2 4200legalized: true 4201regBankSelected: true 4202tracksRegLiveness: true 4203registers: 4204 - { id: 0, class: fpr } 4205 - { id: 1, class: fpr } 4206liveins: 4207 - { reg: '$d0', virtual-reg: '%1' } 4208body: | 4209 bb.0.entry: 4210 liveins: $d0 4211 4212 ; CHECK-LABEL: name: test_rule1622_id2926_at_idx98477 4213 ; CHECK: liveins: $d0 4214 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4215 ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0 4216 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]] 4217 %1:fpr(<4 x s16>) = COPY $d0 4218 %0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>) 4219 $noreg = PATCHABLE_RET %0(<4 x s32>) 4220 4221... 4222--- 4223name: test_rule1623_id2929_at_idx98522 4224alignment: 2 4225legalized: true 4226regBankSelected: true 4227tracksRegLiveness: true 4228registers: 4229 - { id: 0, class: fpr } 4230 - { id: 1, class: fpr } 4231liveins: 4232 - { reg: '$d0', virtual-reg: '%1' } 4233body: | 4234 bb.0.entry: 4235 liveins: $d0 4236 4237 ; CHECK-LABEL: name: test_rule1623_id2929_at_idx98522 4238 ; CHECK: liveins: $d0 4239 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4240 ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0 4241 ; CHECK: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]] 4242 %1:fpr(<2 x s32>) = COPY $d0 4243 %0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>) 4244 $noreg = PATCHABLE_RET %0(<2 x s64>) 4245 4246... 4247--- 4248name: test_rule1632_id687_at_idx98847 4249alignment: 2 4250legalized: true 4251regBankSelected: true 4252tracksRegLiveness: true 4253registers: 4254 - { id: 0, class: fpr } 4255 - { id: 1, class: fpr } 4256liveins: 4257 - { reg: '$d0', virtual-reg: '%1' } 4258body: | 4259 bb.0.entry: 4260 liveins: $d0 4261 4262 ; CHECK-LABEL: name: test_rule1632_id687_at_idx98847 4263 ; CHECK: liveins: $d0 4264 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4265 ; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = SCVTFv2f32 [[COPY]] 4266 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]] 4267 %1:fpr(<2 x s32>) = COPY $d0 4268 %0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>) 4269 $noreg = PATCHABLE_RET %0(<2 x s32>) 4270 4271... 4272--- 4273name: test_rule1633_id688_at_idx98882 4274alignment: 2 4275legalized: true 4276regBankSelected: true 4277tracksRegLiveness: true 4278registers: 4279 - { id: 0, class: fpr } 4280 - { id: 1, class: fpr } 4281liveins: 4282 - { reg: '$q0', virtual-reg: '%1' } 4283body: | 4284 bb.0.entry: 4285 liveins: $q0 4286 4287 ; CHECK-LABEL: name: test_rule1633_id688_at_idx98882 4288 ; CHECK: liveins: $q0 4289 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4290 ; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = SCVTFv4f32 [[COPY]] 4291 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]] 4292 %1:fpr(<4 x s32>) = COPY $q0 4293 %0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>) 4294 $noreg = PATCHABLE_RET %0(<4 x s32>) 4295 4296... 4297--- 4298name: test_rule1634_id689_at_idx98917 4299alignment: 2 4300legalized: true 4301regBankSelected: true 4302tracksRegLiveness: true 4303registers: 4304 - { id: 0, class: fpr } 4305 - { id: 1, class: fpr } 4306liveins: 4307 - { reg: '$q0', virtual-reg: '%1' } 4308body: | 4309 bb.0.entry: 4310 liveins: $q0 4311 4312 ; CHECK-LABEL: name: test_rule1634_id689_at_idx98917 4313 ; CHECK: liveins: $q0 4314 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4315 ; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = SCVTFv2f64 [[COPY]] 4316 ; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]] 4317 %1:fpr(<2 x s64>) = COPY $q0 4318 %0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>) 4319 $noreg = PATCHABLE_RET %0(<2 x s64>) 4320 4321... 4322--- 4323name: test_rule1635_id748_at_idx98952 4324alignment: 2 4325legalized: true 4326regBankSelected: true 4327tracksRegLiveness: true 4328registers: 4329 - { id: 0, class: fpr } 4330 - { id: 1, class: fpr } 4331liveins: 4332 - { reg: '$q0', virtual-reg: '%1' } 4333body: | 4334 bb.0.entry: 4335 liveins: $q0 4336 4337 ; CHECK-LABEL: name: test_rule1635_id748_at_idx98952 4338 ; CHECK: liveins: $q0 4339 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4340 ; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]] 4341 ; CHECK: $noreg = PATCHABLE_RET [[XTNv8i8_]] 4342 %1:fpr(<8 x s16>) = COPY $q0 4343 %0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>) 4344 $noreg = PATCHABLE_RET %0(<8 x s8>) 4345 4346... 4347--- 4348name: test_rule1636_id749_at_idx98987 4349alignment: 2 4350legalized: true 4351regBankSelected: true 4352tracksRegLiveness: true 4353registers: 4354 - { id: 0, class: fpr } 4355 - { id: 1, class: fpr } 4356liveins: 4357 - { reg: '$q0', virtual-reg: '%1' } 4358body: | 4359 bb.0.entry: 4360 liveins: $q0 4361 4362 ; CHECK-LABEL: name: test_rule1636_id749_at_idx98987 4363 ; CHECK: liveins: $q0 4364 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4365 ; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]] 4366 ; CHECK: $noreg = PATCHABLE_RET [[XTNv4i16_]] 4367 %1:fpr(<4 x s32>) = COPY $q0 4368 %0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>) 4369 $noreg = PATCHABLE_RET %0(<4 x s16>) 4370 4371... 4372--- 4373name: test_rule1637_id750_at_idx99022 4374alignment: 2 4375legalized: true 4376regBankSelected: true 4377tracksRegLiveness: true 4378registers: 4379 - { id: 0, class: fpr } 4380 - { id: 1, class: fpr } 4381liveins: 4382 - { reg: '$q0', virtual-reg: '%1' } 4383body: | 4384 bb.0.entry: 4385 liveins: $q0 4386 4387 ; CHECK-LABEL: name: test_rule1637_id750_at_idx99022 4388 ; CHECK: liveins: $q0 4389 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4390 ; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]] 4391 ; CHECK: $noreg = PATCHABLE_RET [[XTNv2i32_]] 4392 %1:fpr(<2 x s64>) = COPY $q0 4393 %0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>) 4394 $noreg = PATCHABLE_RET %0(<2 x s32>) 4395 4396... 4397--- 4398name: test_rule1647_id731_at_idx99386 4399alignment: 2 4400legalized: true 4401regBankSelected: true 4402tracksRegLiveness: true 4403registers: 4404 - { id: 0, class: fpr } 4405 - { id: 1, class: fpr } 4406liveins: 4407 - { reg: '$d0', virtual-reg: '%1' } 4408body: | 4409 bb.0.entry: 4410 liveins: $d0 4411 4412 ; CHECK-LABEL: name: test_rule1647_id731_at_idx99386 4413 ; CHECK: liveins: $d0 4414 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4415 ; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = UCVTFv2f32 [[COPY]] 4416 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]] 4417 %1:fpr(<2 x s32>) = COPY $d0 4418 %0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>) 4419 $noreg = PATCHABLE_RET %0(<2 x s32>) 4420 4421... 4422--- 4423name: test_rule1648_id732_at_idx99421 4424alignment: 2 4425legalized: true 4426regBankSelected: true 4427tracksRegLiveness: true 4428registers: 4429 - { id: 0, class: fpr } 4430 - { id: 1, class: fpr } 4431liveins: 4432 - { reg: '$q0', virtual-reg: '%1' } 4433body: | 4434 bb.0.entry: 4435 liveins: $q0 4436 4437 ; CHECK-LABEL: name: test_rule1648_id732_at_idx99421 4438 ; CHECK: liveins: $q0 4439 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4440 ; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = UCVTFv4f32 [[COPY]] 4441 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]] 4442 %1:fpr(<4 x s32>) = COPY $q0 4443 %0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>) 4444 $noreg = PATCHABLE_RET %0(<4 x s32>) 4445 4446... 4447--- 4448name: test_rule1649_id733_at_idx99456 4449alignment: 2 4450legalized: true 4451regBankSelected: true 4452tracksRegLiveness: true 4453registers: 4454 - { id: 0, class: fpr } 4455 - { id: 1, class: fpr } 4456liveins: 4457 - { reg: '$q0', virtual-reg: '%1' } 4458body: | 4459 bb.0.entry: 4460 liveins: $q0 4461 4462 ; CHECK-LABEL: name: test_rule1649_id733_at_idx99456 4463 ; CHECK: liveins: $q0 4464 ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 4465 ; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = UCVTFv2f64 [[COPY]] 4466 ; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]] 4467 %1:fpr(<2 x s64>) = COPY $q0 4468 %0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>) 4469 $noreg = PATCHABLE_RET %0(<2 x s64>) 4470 4471... 4472--- 4473name: test_rule1650_id2924_at_idx99491 4474alignment: 2 4475legalized: true 4476regBankSelected: true 4477tracksRegLiveness: true 4478registers: 4479 - { id: 0, class: fpr } 4480 - { id: 1, class: fpr } 4481liveins: 4482 - { reg: '$d0', virtual-reg: '%1' } 4483body: | 4484 bb.0.entry: 4485 liveins: $d0 4486 4487 ; CHECK-LABEL: name: test_rule1650_id2924_at_idx99491 4488 ; CHECK: liveins: $d0 4489 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4490 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 4491 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]] 4492 %1:fpr(<8 x s8>) = COPY $d0 4493 %0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>) 4494 $noreg = PATCHABLE_RET %0(<8 x s16>) 4495 4496... 4497--- 4498name: test_rule1651_id2927_at_idx99536 4499alignment: 2 4500legalized: true 4501regBankSelected: true 4502tracksRegLiveness: true 4503registers: 4504 - { id: 0, class: fpr } 4505 - { id: 1, class: fpr } 4506liveins: 4507 - { reg: '$d0', virtual-reg: '%1' } 4508body: | 4509 bb.0.entry: 4510 liveins: $d0 4511 4512 ; CHECK-LABEL: name: test_rule1651_id2927_at_idx99536 4513 ; CHECK: liveins: $d0 4514 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4515 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 4516 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]] 4517 %1:fpr(<4 x s16>) = COPY $d0 4518 %0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>) 4519 $noreg = PATCHABLE_RET %0(<4 x s32>) 4520 4521... 4522--- 4523name: test_rule1652_id2930_at_idx99581 4524alignment: 2 4525legalized: true 4526regBankSelected: true 4527tracksRegLiveness: true 4528registers: 4529 - { id: 0, class: fpr } 4530 - { id: 1, class: fpr } 4531liveins: 4532 - { reg: '$d0', virtual-reg: '%1' } 4533body: | 4534 bb.0.entry: 4535 liveins: $d0 4536 4537 ; CHECK-LABEL: name: test_rule1652_id2930_at_idx99581 4538 ; CHECK: liveins: $d0 4539 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 4540 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 4541 ; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]] 4542 %1:fpr(<2 x s32>) = COPY $d0 4543 %0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>) 4544 $noreg = PATCHABLE_RET %0(<2 x s64>) 4545 4546... 4547