1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6
7  define void @zextload_s32_from_s16(i16 *%addr) { ret void }
8  define void @zextload_s32_from_s16_not_combined(i16 *%addr) { ret void }
9...
10
11---
12name:            zextload_s32_from_s16
13legalized:       true
14regBankSelected: true
15
16body:             |
17  bb.0:
18    liveins: $x0
19
20    ; CHECK-LABEL: name: zextload_s32_from_s16
21    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
22    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
23    ; CHECK: $w0 = COPY [[T0]]
24    %0:gpr(p0) = COPY $x0
25    %1:gpr(s32) = G_ZEXTLOAD %0 :: (load 2 from %ir.addr)
26    $w0 = COPY %1(s32)
27...
28---
29name:            zextload_s32_from_s16_not_combined
30legalized:       true
31regBankSelected: true
32
33body:             |
34  bb.0:
35    liveins: $x0
36
37    ; CHECK-LABEL: name: zextload_s32_from_s16_not_combined
38    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
39    ; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
40    ; CHECK: [[T1:%[0-9]+]]:gpr32 = UBFMWri [[T0]], 0, 15
41    ; CHECK: $w0 = COPY [[T1]]
42    %0:gpr(p0) = COPY $x0
43    %1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
44    %2:gpr(s32) = G_ZEXT %1
45    $w0 = COPY %2(s32)
46...
47