1; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin < %s | FileCheck %s
2; RUN: llc %s -O0 -fast-isel -fast-isel-abort=1 -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
3; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
4
5; CHECK-SSA-LABEL: Machine code for function t1
6
7; CHECK-SSA: [[QUOTREG:%[0-9]+]]:gpr32 = SDIVWr
8; CHECK-SSA-NOT: [[QUOTREG]] =
9; CHECK-SSA: {{%[0-9]+}}:gpr32 = MSUBWrrr killed [[QUOTREG]]
10
11; CHECK-SSA-LABEL: Machine code for function t2
12
13define i32 @t1(i32 %a, i32 %b) {
14; CHECK: @t1
15; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
16; CHECK: msub w0, [[TMP]], w1, w0
17  %1 = srem i32 %a, %b
18  ret i32 %1
19}
20
21define i64 @t2(i64 %a, i64 %b) {
22; CHECK: @t2
23; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
24; CHECK: msub x0, [[TMP]], x1, x0
25  %1 = srem i64 %a, %b
26  ret i64 %1
27}
28
29define i32 @t3(i32 %a, i32 %b) {
30; CHECK: @t3
31; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
32; CHECK: msub w0, [[TMP]], w1, w0
33  %1 = urem i32 %a, %b
34  ret i32 %1
35}
36
37define i64 @t4(i64 %a, i64 %b) {
38; CHECK: @t4
39; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
40; CHECK: msub x0, [[TMP]], x1, x0
41  %1 = urem i64 %a, %b
42  ret i64 %1
43}
44