1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-eabi | FileCheck %s
3
4;==--------------------------------------------------------------------------==
5; Tests for MOV-immediate implemented with ORR-immediate.
6;==--------------------------------------------------------------------------==
7
8; 64-bit immed with 32-bit pattern size, rotated by 0.
9define i64 @test64_32_rot0() nounwind {
10; CHECK-LABEL: test64_32_rot0:
11; CHECK:       // %bb.0:
12; CHECK-NEXT:    mov x0, #30064771079
13; CHECK-NEXT:    ret
14  ret i64 30064771079
15}
16
17; 64-bit immed with 32-bit pattern size, rotated by 2.
18define i64 @test64_32_rot2() nounwind {
19; CHECK-LABEL: test64_32_rot2:
20; CHECK:       // %bb.0:
21; CHECK-NEXT:    mov x0, #-4611686002321260541
22; CHECK-NEXT:    ret
23  ret i64 13835058071388291075
24}
25
26; 64-bit immed with 4-bit pattern size, rotated by 3.
27define i64 @test64_4_rot3() nounwind {
28; CHECK-LABEL: test64_4_rot3:
29; CHECK:       // %bb.0:
30; CHECK-NEXT:    mov x0, #-1229782938247303442
31; CHECK-NEXT:    ret
32  ret i64 17216961135462248174
33}
34
35; 64-bit immed with 64-bit pattern size, many bits.
36define i64 @test64_64_manybits() nounwind {
37; CHECK-LABEL: test64_64_manybits:
38; CHECK:       // %bb.0:
39; CHECK-NEXT:    mov x0, #4503599627304960
40; CHECK-NEXT:    ret
41  ret i64 4503599627304960
42}
43
44; 64-bit immed with 64-bit pattern size, one bit.
45; FIXME: Prefer movz, so it prints as "mov".
46define i64 @test64_64_onebit() nounwind {
47; CHECK-LABEL: test64_64_onebit:
48; CHECK:       // %bb.0:
49; CHECK-NEXT:    orr x0, xzr, #0x4000000000
50; CHECK-NEXT:    ret
51  ret i64 274877906944
52}
53
54; 32-bit immed with 32-bit pattern size, rotated by 16.
55; FIXME: Prefer "movz" instead (so we print as "mov").
56define i32 @test32_32_rot16() nounwind {
57; CHECK-LABEL: test32_32_rot16:
58; CHECK:       // %bb.0:
59; CHECK-NEXT:    orr w0, wzr, #0xff0000
60; CHECK-NEXT:    ret
61  ret i32 16711680
62}
63
64; 32-bit immed with 2-bit pattern size, rotated by 1.
65define i32 @test32_2_rot1() nounwind {
66; CHECK-LABEL: test32_2_rot1:
67; CHECK:       // %bb.0:
68; CHECK-NEXT:    mov w0, #-1431655766
69; CHECK-NEXT:    ret
70  ret i32 2863311530
71}
72
73;==--------------------------------------------------------------------------==
74; Tests for MOVZ with MOVK.
75;==--------------------------------------------------------------------------==
76
77define i32 @movz() nounwind {
78; CHECK-LABEL: movz:
79; CHECK:       // %bb.0:
80; CHECK-NEXT:    mov w0, #5
81; CHECK-NEXT:    ret
82  ret i32 5
83}
84
85define i64 @movz_3movk() nounwind {
86; CHECK-LABEL: movz_3movk:
87; CHECK:       // %bb.0:
88; CHECK-NEXT:    mov x0, #22136
89; CHECK-NEXT:    movk x0, #43981, lsl #16
90; CHECK-NEXT:    movk x0, #4660, lsl #32
91; CHECK-NEXT:    movk x0, #5, lsl #48
92; CHECK-NEXT:    ret
93  ret i64 1427392313513592
94}
95
96define i64 @movz_movk_skip1() nounwind {
97; CHECK-LABEL: movz_movk_skip1:
98; CHECK:       // %bb.0:
99; CHECK-NEXT:    mov x0, #1126236160
100; CHECK-NEXT:    movk x0, #5, lsl #32
101; CHECK-NEXT:    ret
102  ret i64 22601072640
103}
104
105define i64 @movz_skip1_movk() nounwind {
106; CHECK-LABEL: movz_skip1_movk:
107; CHECK:       // %bb.0:
108; CHECK-NEXT:    mov x0, #4660
109; CHECK-NEXT:    movk x0, #34388, lsl #32
110; CHECK-NEXT:    ret
111  ret i64 147695335379508
112}
113
114; FIXME: Prefer "mov w0, #2863311530; lsl x0, x0, #4"
115; or "mov x0, #-6148914691236517206; and x0, x0, #45812984480"
116define i64 @orr_lsl_pattern() nounwind {
117; CHECK-LABEL: orr_lsl_pattern:
118; CHECK:       // %bb.0:
119; CHECK-NEXT:    mov x0, #43680
120; CHECK-NEXT:    movk x0, #43690, lsl #16
121; CHECK-NEXT:    movk x0, #10, lsl #32
122; CHECK-NEXT:    ret
123  ret i64 45812984480
124}
125
126; FIXME: prefer "mov x0, #-16639; lsl x0, x0, #24"
127define i64 @mvn_lsl_pattern() nounwind {
128; CHECK-LABEL: mvn_lsl_pattern:
129; CHECK:       // %bb.0:
130; CHECK-NEXT:    mov x0, #16777216
131; CHECK-NEXT:    movk x0, #65471, lsl #32
132; CHECK-NEXT:    movk x0, #65535, lsl #48
133; CHECK-NEXT:    ret
134  ret i64 -279156097024
135}
136
137; FIXME: prefer "mov w0, #-63; movk x0, #17, lsl #32"
138define i64 @mvn32_pattern_2() nounwind {
139; CHECK-LABEL: mvn32_pattern_2:
140; CHECK:       // %bb.0:
141; CHECK-NEXT:    mov x0, #65473
142; CHECK-NEXT:    movk x0, #65535, lsl #16
143; CHECK-NEXT:    movk x0, #17, lsl #32
144; CHECK-NEXT:    ret
145  ret i64 77309411265
146}
147
148;==--------------------------------------------------------------------------==
149; Tests for MOVN with MOVK.
150;==--------------------------------------------------------------------------==
151
152define i64 @movn() nounwind {
153; CHECK-LABEL: movn:
154; CHECK:       // %bb.0:
155; CHECK-NEXT:    mov x0, #-42
156; CHECK-NEXT:    ret
157  ret i64 -42
158}
159
160define i64 @movn_skip1_movk() nounwind {
161; CHECK-LABEL: movn_skip1_movk:
162; CHECK:       // %bb.0:
163; CHECK-NEXT:    mov x0, #-60876
164; CHECK-NEXT:    movk x0, #65494, lsl #32
165; CHECK-NEXT:    ret
166  ret i64 -176093720012
167}
168
169;==--------------------------------------------------------------------------==
170; Tests for ORR with MOVK.
171;==--------------------------------------------------------------------------==
172; rdar://14987673
173
174define i64 @orr_movk1() nounwind {
175; CHECK-LABEL: orr_movk1:
176; CHECK:       // %bb.0:
177; CHECK-NEXT:    mov x0, #72056494543077120
178; CHECK-NEXT:    movk x0, #57005, lsl #16
179; CHECK-NEXT:    ret
180  ret i64 72056498262245120
181}
182
183define i64 @orr_movk2() nounwind {
184; CHECK-LABEL: orr_movk2:
185; CHECK:       // %bb.0:
186; CHECK-NEXT:    mov x0, #72056494543077120
187; CHECK-NEXT:    movk x0, #57005, lsl #48
188; CHECK-NEXT:    ret
189  ret i64 -2400982650836746496
190}
191
192define i64 @orr_movk3() nounwind {
193; CHECK-LABEL: orr_movk3:
194; CHECK:       // %bb.0:
195; CHECK-NEXT:    mov x0, #72056494543077120
196; CHECK-NEXT:    movk x0, #57005, lsl #32
197; CHECK-NEXT:    ret
198  ret i64 72020953688702720
199}
200
201define i64 @orr_movk4() nounwind {
202; CHECK-LABEL: orr_movk4:
203; CHECK:       // %bb.0:
204; CHECK-NEXT:    mov x0, #72056494543077120
205; CHECK-NEXT:    movk x0, #57005
206; CHECK-NEXT:    ret
207  ret i64 72056494543068845
208}
209
210; rdar://14987618
211define i64 @orr_movk5() nounwind {
212; CHECK-LABEL: orr_movk5:
213; CHECK:       // %bb.0:
214; CHECK-NEXT:    mov x0, #-71777214294589696
215; CHECK-NEXT:    movk x0, #57005, lsl #16
216; CHECK-NEXT:    ret
217  ret i64 -71777214836900096
218}
219
220define i64 @orr_movk6() nounwind {
221; CHECK-LABEL: orr_movk6:
222; CHECK:       // %bb.0:
223; CHECK-NEXT:    mov x0, #-71777214294589696
224; CHECK-NEXT:    movk x0, #57005, lsl #16
225; CHECK-NEXT:    movk x0, #57005, lsl #48
226; CHECK-NEXT:    ret
227  ret i64 -2400982647117578496
228}
229
230define i64 @orr_movk7() nounwind {
231; CHECK-LABEL: orr_movk7:
232; CHECK:       // %bb.0:
233; CHECK-NEXT:    mov x0, #-71777214294589696
234; CHECK-NEXT:    movk x0, #57005, lsl #48
235; CHECK-NEXT:    ret
236  ret i64 -2400982646575268096
237}
238
239define i64 @orr_movk8() nounwind {
240; CHECK-LABEL: orr_movk8:
241; CHECK:       // %bb.0:
242; CHECK-NEXT:    mov x0, #-71777214294589696
243; CHECK-NEXT:    movk x0, #57005
244; CHECK-NEXT:    movk x0, #57005, lsl #48
245; CHECK-NEXT:    ret
246  ret i64 -2400982646575276371
247}
248
249; rdar://14987715
250define i64 @orr_movk9() nounwind {
251; CHECK-LABEL: orr_movk9:
252; CHECK:       // %bb.0:
253; CHECK-NEXT:    mov x0, #1152921435887370240
254; CHECK-NEXT:    movk x0, #65280
255; CHECK-NEXT:    movk x0, #57005, lsl #16
256; CHECK-NEXT:    ret
257  ret i64 1152921439623315200
258}
259
260define i64 @orr_movk10() nounwind {
261; CHECK-LABEL: orr_movk10:
262; CHECK:       // %bb.0:
263; CHECK-NEXT:    mov x0, #1152921504606846720
264; CHECK-NEXT:    movk x0, #57005, lsl #16
265; CHECK-NEXT:    ret
266  ret i64 1152921504047824640
267}
268
269define i64 @orr_movk11() nounwind {
270; CHECK-LABEL: orr_movk11:
271; CHECK:       // %bb.0:
272; CHECK-NEXT:    mov x0, #-65281
273; CHECK-NEXT:    movk x0, #57005, lsl #16
274; CHECK-NEXT:    movk x0, #65520, lsl #48
275; CHECK-NEXT:    ret
276  ret i64 -4222125209747201
277}
278
279define i64 @orr_movk12() nounwind {
280; CHECK-LABEL: orr_movk12:
281; CHECK:       // %bb.0:
282; CHECK-NEXT:    mov x0, #-4503599627370241
283; CHECK-NEXT:    movk x0, #57005, lsl #32
284; CHECK-NEXT:    ret
285  ret i64 -4258765016661761
286}
287
288define i64 @orr_movk13() nounwind {
289; CHECK-LABEL: orr_movk13:
290; CHECK:       // %bb.0:
291; CHECK-NEXT:    mov x0, #17592169267200
292; CHECK-NEXT:    movk x0, #57005
293; CHECK-NEXT:    movk x0, #57005, lsl #48
294; CHECK-NEXT:    ret
295  ret i64 -2401245434149282131
296}
297
298; rdar://13944082
299define i64 @g() nounwind {
300; CHECK-LABEL: g:
301; CHECK:       // %bb.0: // %entry
302; CHECK-NEXT:    mov x0, #2
303; CHECK-NEXT:    movk x0, #65535, lsl #48
304; CHECK-NEXT:    ret
305entry:
306  ret i64 -281474976710654
307}
308
309define i64 @orr_movk14() nounwind {
310; CHECK-LABEL: orr_movk14:
311; CHECK:       // %bb.0:
312; CHECK-NEXT:    mov x0, #-549755813888
313; CHECK-NEXT:    movk x0, #2048, lsl #16
314; CHECK-NEXT:    ret
315  ret i64 -549621596160
316}
317
318define i64 @orr_movk15() nounwind {
319; CHECK-LABEL: orr_movk15:
320; CHECK:       // %bb.0:
321; CHECK-NEXT:    mov x0, #549755813887
322; CHECK-NEXT:    movk x0, #63487, lsl #16
323; CHECK-NEXT:    ret
324  ret i64 549621596159
325}
326
327; FIXME: prefer "mov x0, #2147483646; orr x0, x0, #36028659580010496"
328define i64 @orr_movk16() nounwind {
329; CHECK-LABEL: orr_movk16:
330; CHECK:       // %bb.0:
331; CHECK-NEXT:    mov x0, #36028659580010496
332; CHECK-NEXT:    movk x0, #65534
333; CHECK-NEXT:    movk x0, #32767, lsl #16
334; CHECK-NEXT:    ret
335  ret i64 36028661727494142
336}
337
338define i64 @orr_movk17() nounwind {
339; CHECK-LABEL: orr_movk17:
340; CHECK:       // %bb.0:
341; CHECK-NEXT:    mov x0, #-1099511627776
342; CHECK-NEXT:    movk x0, #65280, lsl #16
343; CHECK-NEXT:    ret
344  ret i64 -1095233437696
345}
346
347define i64 @orr_movk18() nounwind {
348; CHECK-LABEL: orr_movk18:
349; CHECK:       // %bb.0:
350; CHECK-NEXT:    mov x0, #137438887936
351; CHECK-NEXT:    movk x0, #65473
352; CHECK-NEXT:    ret
353  ret i64 137438953409
354}
355
356; FIXME: prefer "mov x0, #72340172838076673; and x0, x0, #2199023255296"
357define i64 @orr_and() nounwind {
358; CHECK-LABEL: orr_and:
359; CHECK:       // %bb.0:
360; CHECK-NEXT:    mov x0, #256
361; CHECK-NEXT:    movk x0, #257, lsl #16
362; CHECK-NEXT:    movk x0, #257, lsl #32
363; CHECK-NEXT:    ret
364  ret i64 1103823438080
365}
366
367; FIXME: prefer "mov w0, #-1431655766; movk x0, #9, lsl #32"
368define i64 @movn_movk() nounwind {
369; CHECK-LABEL: movn_movk:
370; CHECK:       // %bb.0:
371; CHECK-NEXT:    mov x0, #43690
372; CHECK-NEXT:    movk x0, #43690, lsl #16
373; CHECK-NEXT:    movk x0, #9, lsl #32
374; CHECK-NEXT:    ret
375  ret i64 41518017194
376}
377
378; FIXME: prefer "mov w0, #-13690; orr x0, x0, #0x1111111111111111"
379define i64 @movn_orr() nounwind {
380; CHECK-LABEL: movn_orr:
381; CHECK:       // %bb.0:
382; CHECK-NEXT:    mov x0, #-51847
383; CHECK-NEXT:    movk x0, #4369, lsl #32
384; CHECK-NEXT:    movk x0, #4369, lsl #48
385; CHECK-NEXT:    ret
386  ret i64 1229782942255887737
387}
388
389; FIXME: prefer "mov w0, #-305397761; eor x0, x0, #0x3333333333333333"
390define i64 @movn_eor() nounwind {
391; CHECK-LABEL: movn_eor:
392; CHECK:       // %bb.0:
393; CHECK-NEXT:    mov x0, #3689348814741910323
394; CHECK-NEXT:    movk x0, #52428
395; CHECK-NEXT:    movk x0, #8455, lsl #16
396; CHECK-NEXT:    ret
397  ret i64 3689348814437076172
398}
399
400; FIXME: prefer "mov x0, #536866816; orr x0, x0, #0x3fff800000000000"
401define i64 @orr_orr_64() nounwind {
402; CHECK-LABEL: orr_orr_64:
403; CHECK:       // %bb.0:
404; CHECK-NEXT:    mov x0, #4611545280939032576
405; CHECK-NEXT:    movk x0, #61440
406; CHECK-NEXT:    movk x0, #8191, lsl #16
407; CHECK-NEXT:    ret
408  ret i64 4611545281475899392
409}
410
411; FIXME: prefer "mov x0, #558551907040256; orr x0, x0, #0x1000100010001000"
412define i64 @orr_orr_32() nounwind {
413; CHECK-LABEL: orr_orr_32:
414; CHECK:       // %bb.0:
415; CHECK-NEXT:    mov x0, #-287953294993589248
416; CHECK-NEXT:    movk x0, #7169, lsl #16
417; CHECK-NEXT:    movk x0, #7169, lsl #48
418; CHECK-NEXT:    ret
419  ret i64 2018171185438784512
420}
421
422; FIXME: prefer "mov x0, #281479271743489; orr x0, x0, #0x1000100010001000"
423define i64 @orr_orr_16() nounwind {
424; CHECK-LABEL: orr_orr_16:
425; CHECK:       // %bb.0:
426; CHECK-NEXT:    mov x0, #4097
427; CHECK-NEXT:    movk x0, #4097, lsl #16
428; CHECK-NEXT:    movk x0, #4097, lsl #32
429; CHECK-NEXT:    movk x0, #4097, lsl #48
430; CHECK-NEXT:    ret
431  ret i64 1153220576333074433
432}
433
434; FIXME: prefer "mov x0, #144680345676153346; orr x0, x0, #0x1818181818181818"
435define i64 @orr_orr_8() nounwind {
436; CHECK-LABEL: orr_orr_8:
437; CHECK:       // %bb.0:
438; CHECK-NEXT:    mov x0, #6682
439; CHECK-NEXT:    movk x0, #6682, lsl #16
440; CHECK-NEXT:    movk x0, #6682, lsl #32
441; CHECK-NEXT:    movk x0, #6682, lsl #48
442; CHECK-NEXT:    ret
443  ret i64 1880844493789993498
444}
445
446; FIXME: prefer "mov x0, #-6148914691236517206; orr x0, x0, #0x0FFFFF0000000000"
447define i64 @orr_64_orr_8() nounwind {
448; CHECK-LABEL: orr_64_orr_8:
449; CHECK:       // %bb.0:
450; CHECK-NEXT:    mov x0, #-6148914691236517206
451; CHECK-NEXT:    movk x0, #65450, lsl #32
452; CHECK-NEXT:    movk x0, #45055, lsl #48
453; CHECK-NEXT:    ret
454  ret i64 -5764607889538110806
455}
456