1; RUN: llc -mtriple=arm64-apple-ios   -mcpu=cyclone   < %s | FileCheck %s -check-prefixes=ALL,CYCLONE
2; RUN: llc -mtriple=arm64-apple-ios   -mcpu=cyclone -mattr=+fullfp16 < %s | FileCheck %s -check-prefixes=CYCLONE-FULLFP16
3; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m1 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
4; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=exynos-m3 < %s | FileCheck %s -check-prefixes=ALL,OTHERS
5; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=kryo      < %s | FileCheck %s -check-prefixes=ALL,OTHERS
6; RUN: llc -mtriple=aarch64-gnu-linux -mcpu=falkor    < %s | FileCheck %s -check-prefixes=ALL,OTHERS
7
8declare void @bar(half, float, double, <2 x double>)
9declare void @bari(i32, i32)
10declare void @barl(i64, i64)
11declare void @barf(float, float)
12
13define void @t1() nounwind ssp {
14entry:
15; ALL-LABEL: t1:
16; ALL-NOT: fmov
17; ALL:     ldr h0,{{.*}}
18; CYCLONE: fmov s1, wzr
19; CYCLONE: fmov d2, xzr
20; CYCLONE: movi.16b v3, #0
21; CYCLONE-FULLFP16: fmov h0, wzr
22; CYCLONE-FULLFP16: fmov s1, wzr
23; CYCLONE-FULLFP16: fmov d2, xzr
24; CYCLONE-FULLFP16: movi.16b v3, #0
25; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
26; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
27; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
28  tail call void @bar(half 0.000000e+00, float 0.000000e+00, double 0.000000e+00, <2 x double> <double 0.000000e+00, double 0.000000e+00>) nounwind
29  ret void
30}
31
32define void @t2() nounwind ssp {
33entry:
34; ALL-LABEL: t2:
35; ALL-NOT: mov w0, wzr
36; ALL: mov w{{[0-3]+}}, #0
37; ALL: mov w{{[0-3]+}}, #0
38  tail call void @bari(i32 0, i32 0) nounwind
39  ret void
40}
41
42define void @t3() nounwind ssp {
43entry:
44; ALL-LABEL: t3:
45; ALL-NOT: mov x0, xzr
46; ALL: mov x{{[0-3]+}}, #0
47; ALL: mov x{{[0-3]+}}, #0
48  tail call void @barl(i64 0, i64 0) nounwind
49  ret void
50}
51
52define void @t4() nounwind ssp {
53; ALL-LABEL: t4:
54; ALL-NOT: fmov
55; CYCLONE: fmov s{{[0-3]+}}, wzr
56; CYCLONE: fmov s{{[0-3]+}}, wzr
57; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
58; CYCLONE-FULLFP16: fmov s{{[0-3]+}}, wzr
59; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
60; OTHERS: movi v{{[0-3]+}}.2d, #0000000000000000
61  tail call void @barf(float 0.000000e+00, float 0.000000e+00) nounwind
62  ret void
63}
64
65; We used to produce spills+reloads for a Q register with zero cycle zeroing
66; enabled.
67; ALL-LABEL: foo:
68; ALL-NOT: str q{{[0-9]+}}
69; ALL-NOT: ldr q{{[0-9]+}}
70define double @foo(i32 %n) {
71entry:
72  br label %for.body
73
74for.body:
75  %phi0 = phi double [ 1.0, %entry ], [ %v0, %for.body ]
76  %i.076 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
77  %conv21 = sitofp i32 %i.076 to double
78  %call = tail call fast double @sin(double %conv21)
79  %cmp.i = fcmp fast olt double %phi0, %call
80  %v0 = select i1 %cmp.i, double %call, double %phi0
81  %inc = add nuw nsw i32 %i.076, 1
82  %cmp = icmp slt i32 %inc, %n
83  br i1 %cmp, label %for.body, label %for.end
84
85for.end:
86  ret double %v0
87}
88
89define <2 x i64> @t6() {
90; ALL-LABEL: t6:
91; CYCLONE: movi.16b v0, #0
92; OTHERS: movi v0.2d, #0000000000000000
93 ret <2 x i64> zeroinitializer
94}
95
96
97declare double @sin(double)
98