1; RUN: llc -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s | FileCheck %s 2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=2 -verify-machineinstrs < %s | FileCheck %s 3 4; Vector Integer Add 5define <8 x i8> @add_v8i8_rr(<8 x i8> %a, <8 x i8> %b) { 6; CHECK: add_v8i8_rr 7; CHECK: add.8b v0, v0, v1 8 %1 = add <8 x i8> %a, %b 9 ret <8 x i8> %1 10} 11 12define <16 x i8> @add_v16i8_rr(<16 x i8> %a, <16 x i8> %b) { 13; CHECK: add_v16i8_rr 14; CHECK: add.16b v0, v0, v1 15 %1 = add <16 x i8> %a, %b 16 ret <16 x i8> %1 17} 18 19define <4 x i16> @add_v4i16_rr(<4 x i16> %a, <4 x i16> %b) { 20; CHECK: add_v4i16_rr 21; CHECK: add.4h v0, v0, v1 22 %1 = add <4 x i16> %a, %b 23 ret <4 x i16> %1 24} 25 26define <8 x i16> @add_v8i16_rr(<8 x i16> %a, <8 x i16> %b) { 27; CHECK: add_v8i16_rr 28; CHECK: add.8h v0, v0, v1 29 %1 = add <8 x i16> %a, %b 30 ret <8 x i16> %1 31} 32 33define <2 x i32> @add_v2i32_rr(<2 x i32> %a, <2 x i32> %b) { 34; CHECK: add_v2i32_rr 35; CHECK: add.2s v0, v0, v1 36 %1 = add <2 x i32> %a, %b 37 ret <2 x i32> %1 38} 39 40define <4 x i32> @add_v4i32_rr(<4 x i32> %a, <4 x i32> %b) { 41; CHECK: add_v4i32_rr 42; CHECK: add.4s v0, v0, v1 43 %1 = add <4 x i32> %a, %b 44 ret <4 x i32> %1 45} 46 47define <2 x i64> @add_v2i64_rr(<2 x i64> %a, <2 x i64> %b) { 48; CHECK: add_v2i64_rr 49; CHECK: add.2d v0, v0, v1 50 %1 = add <2 x i64> %a, %b 51 ret <2 x i64> %1 52} 53 54; Vector Floating-point Add 55define <2 x float> @add_v2f32_rr(<2 x float> %a, <2 x float> %b) { 56; CHECK: add_v2f32_rr 57; CHECK: fadd.2s v0, v0, v1 58 %1 = fadd <2 x float> %a, %b 59 ret <2 x float> %1 60} 61 62define <4 x float> @add_v4f32_rr(<4 x float> %a, <4 x float> %b) { 63; CHECK: add_v4f32_rr 64; CHECK: fadd.4s v0, v0, v1 65 %1 = fadd <4 x float> %a, %b 66 ret <4 x float> %1 67} 68 69define <2 x double> @add_v2f64_rr(<2 x double> %a, <2 x double> %b) { 70; CHECK: add_v2f64_rr 71; CHECK: fadd.2d v0, v0, v1 72 %1 = fadd <2 x double> %a, %b 73 ret <2 x double> %1 74} 75