1; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2
3define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) {
4; CHECK-LABEL: test_vext_s8:
5; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
6entry:
7  %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
8  ret <8 x i8> %vext
9}
10
11define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) {
12; CHECK-LABEL: test_vext_s16:
13; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
14entry:
15  %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
16  ret <4 x i16> %vext
17}
18
19define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) {
20; CHECK-LABEL: test_vext_s32:
21; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
22entry:
23  %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
24  ret <2 x i32> %vext
25}
26
27define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) {
28; CHECK-LABEL: test_vext_s64:
29; CHECK-NOT: ext {{v[0-9]+}}
30entry:
31  %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
32  ret <1 x i64> %vext
33}
34
35define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) {
36; CHECK-LABEL: test_vextq_s8:
37; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
38entry:
39  %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
40  ret <16 x i8> %vext
41}
42
43define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) {
44; CHECK-LABEL: test_vextq_s16:
45; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
46entry:
47  %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
48  ret <8 x i16> %vext
49}
50
51define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) {
52; CHECK-LABEL: test_vextq_s32:
53; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
54entry:
55  %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
56  ret <4 x i32> %vext
57}
58
59define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) {
60; CHECK-LABEL: test_vextq_s64:
61; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
62entry:
63  %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
64  ret <2 x i64> %vext
65}
66
67define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) {
68; CHECK-LABEL: test_vext_u8:
69; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
70entry:
71  %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
72  ret <8 x i8> %vext
73}
74
75define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) {
76; CHECK-LABEL: test_vext_u16:
77; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
78entry:
79  %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
80  ret <4 x i16> %vext
81}
82
83define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) {
84; CHECK-LABEL: test_vext_u32:
85; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
86entry:
87  %vext = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 2>
88  ret <2 x i32> %vext
89}
90
91define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) {
92; CHECK-LABEL: test_vext_u64:
93entry:
94  %vext = shufflevector <1 x i64> %a, <1 x i64> %b, <1 x i32> <i32 0>
95  ret <1 x i64> %vext
96}
97
98define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) {
99; CHECK-LABEL: test_vextq_u8:
100; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
101entry:
102  %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
103  ret <16 x i8> %vext
104}
105
106define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) {
107; CHECK-LABEL: test_vextq_u16:
108; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
109entry:
110  %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
111  ret <8 x i16> %vext
112}
113
114define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) {
115; CHECK-LABEL: test_vextq_u32:
116; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
117entry:
118  %vext = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
119  ret <4 x i32> %vext
120}
121
122define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) {
123; CHECK-LABEL: test_vextq_u64:
124; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
125entry:
126  %vext = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 2>
127  ret <2 x i64> %vext
128}
129
130define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) {
131; CHECK-LABEL: test_vext_f32:
132; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
133entry:
134  %vext = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 2>
135  ret <2 x float> %vext
136}
137
138define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) {
139; CHECK-LABEL: test_vext_f64:
140; CHECK-NOT: ext {{v[0-9]+}}
141entry:
142  %vext = shufflevector <1 x double> %a, <1 x double> %b, <1 x i32> <i32 0>
143  ret <1 x double> %vext
144}
145
146define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) {
147; CHECK-LABEL: test_vextq_f32:
148; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x4|4}}
149entry:
150  %vext = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
151  ret <4 x float> %vext
152}
153
154define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) {
155; CHECK-LABEL: test_vextq_f64:
156; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x8|8}}
157entry:
158  %vext = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 2>
159  ret <2 x double> %vext
160}
161
162define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) {
163; CHECK-LABEL: test_vext_p8:
164; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
165entry:
166  %vext = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
167  ret <8 x i8> %vext
168}
169
170define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) {
171; CHECK-LABEL: test_vext_p16:
172; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x6|6}}
173entry:
174  %vext = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
175  ret <4 x i16> %vext
176}
177
178define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) {
179; CHECK-LABEL: test_vextq_p8:
180; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x2|2}}
181entry:
182  %vext = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
183  ret <16 x i8> %vext
184}
185
186define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) {
187; CHECK-LABEL: test_vextq_p16:
188; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
189entry:
190  %vext = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
191  ret <8 x i16> %vext
192}
193
194define <8 x i8> @test_undef_vext_s8(<8 x i8> %a) {
195; CHECK-LABEL: test_undef_vext_s8:
196; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x2|2}}
197entry:
198  %vext = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 10, i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
199  ret <8 x i8> %vext
200}
201
202define <16 x i8> @test_undef_vextq_s8(<16 x i8> %a) {
203; CHECK-LABEL: test_undef_vextq_s8:
204; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
205entry:
206  %vext = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 20, i32 20, i32 20, i32 20, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 20, i32 20, i32 20, i32 20, i32 20>
207  ret <16 x i8> %vext
208}
209
210define <4 x i16> @test_undef_vext_s16(<4 x i16> %a) {
211; CHECK-LABEL: test_undef_vext_s16:
212; CHECK: ext {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #{{0x4|4}}
213entry:
214  %vext = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 5>
215  ret <4 x i16> %vext
216}
217
218define <8 x i16> @test_undef_vextq_s16(<8 x i16> %a) {
219; CHECK-LABEL: test_undef_vextq_s16:
220; CHECK: ext {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #{{0x6|6}}
221entry:
222  %vext = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 10, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
223  ret <8 x i16> %vext
224}
225