1; REQUIRES: arm-registered-target
2; REQUIRES: asserts
3; RUN: llc -o /dev/null %s -debug-only=legalize-types 2>&1 | FileCheck %s
4
5; This test check that when v4f64 gets broken down to two v2f64 it maintains
6; the "nnan" flags.
7
8; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR
9; CHECK-NEXT: Analyzing result type: v4f64
10; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
11
12; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
13; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
14; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan reassoc [[VTWO]], [[VTWO]]
15
16target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
17target triple = "aarch64--linux-gnu"
18
19
20; Function Attrs: norecurse nounwind
21define fastcc double @test() unnamed_addr #1 {
22entry:
23 %0 = insertelement <4 x double> undef, double 1.0, i32 0
24 %1 = insertelement <4 x double> %0, double 1.0, i32 1
25 %2 = insertelement <4 x double> %1, double 1.0, i32 2
26 %3 = insertelement <4 x double> %2, double 1.0, i32 3
27 %4 = call nnan reassoc double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
28 ret double %4
29}
30
31declare double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double>)
32