1# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
2
3--- |
4  define amdgpu_kernel void @constant(i32 addrspace(1)* %global0, i64 addrspace(1)* %global1) {ret void}
5...
6---
7
8name:            constant
9legalized:       true
10regBankSelected: true
11
12
13body: |
14  bb.0:
15    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
16    ; GCN-LABEL: name: constant
17    %0:vgpr(s64) = COPY $vgpr0_vgpr1
18    %1:vgpr(s64) = COPY $vgpr2_vgpr3
19
20    ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1
21    %2:sreg_32(s32) = G_CONSTANT i32 1
22
23    ; GCN: [[LO0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
24    ; GCN: [[HI0:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1
25    ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO0]], %subreg.sub0, [[HI0]], %subreg.sub1
26    %3:sgpr(s64) = G_CONSTANT i64 4294967296
27
28    ; GCN: %{{[0-9]+}}:sreg_32 = S_MOV_B32 1065353216
29    %4:sgpr(s32) = G_FCONSTANT float 1.0
30
31    ; GCN: [[LO1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0
32    ; GCN: [[HI1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1072693248
33    ; GCN: %{{[0-9]+}}:sreg_64_xexec = REG_SEQUENCE [[LO1]], %subreg.sub0, [[HI1]], %subreg.sub1
34    %5:sgpr(s64) = G_FCONSTANT double 1.0
35
36    ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1
37    %6:vgpr(s32) = G_CONSTANT i32 1
38
39    ; GCN: [[LO2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
40    ; GCN: [[HI2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1
41    ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO2]], %subreg.sub0, [[HI2]], %subreg.sub1
42    %7:vgpr(s64) = G_CONSTANT i64 4294967296
43
44    ; GCN: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32 1065353216
45    %8:vgpr(s32) = G_FCONSTANT float 1.0
46
47    ; GCN: [[LO3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0
48    ; GCN: [[HI3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1072693248
49    ; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
50    %9:vgpr(s64) = G_FCONSTANT double 1.0
51
52    G_STORE %2, %0 :: (volatile store 4 into %ir.global0)
53    G_STORE %4, %0 :: (volatile store 4 into %ir.global0)
54    G_STORE %6, %0 :: (volatile store 4 into %ir.global0)
55    G_STORE %8, %0 :: (volatile store 4 into %ir.global0)
56    G_STORE %3, %1 :: (volatile store 8 into %ir.global1)
57    G_STORE %5, %1 :: (volatile store 8 into %ir.global1)
58    G_STORE %7, %1 :: (volatile store 8 into %ir.global1)
59    G_STORE %9, %1 :: (volatile store 8 into %ir.global1)
60...
61---
62