1; FIXME: Need to add support for mubuf stores to enable this on SI.
2; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
3; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s
4; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
5
6; REQUIRES: global-isel
7
8; SMRD load with an immediate offset.
9; GCN-LABEL: {{^}}smrd0:
10; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
11; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
12define amdgpu_kernel void @smrd0(i32 addrspace(4)* %ptr) {
13entry:
14  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 1
15  %1 = load i32, i32 addrspace(4)* %0
16  store i32 %1, i32 addrspace(1)* undef
17  ret void
18}
19
20; SMRD load with the largest possible immediate offset.
21; GCN-LABEL: {{^}}smrd1:
22; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
23; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
24define amdgpu_kernel void @smrd1(i32 addrspace(4)* %ptr) {
25entry:
26  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 255
27  %1 = load i32, i32 addrspace(4)* %0
28  store i32 %1, i32 addrspace(1)* undef
29  ret void
30}
31
32; SMRD load with an offset greater than the largest possible immediate.
33; GCN-LABEL: {{^}}smrd2:
34; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
35; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
36; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
37; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
38; GCN: s_endpgm
39define amdgpu_kernel void @smrd2(i32 addrspace(4)* %ptr) {
40entry:
41  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 256
42  %1 = load i32, i32 addrspace(4)* %0
43  store i32 %1, i32 addrspace(1)* undef
44  ret void
45}
46
47; SMRD load with a 64-bit offset
48; GCN-LABEL: {{^}}smrd3:
49; FIXME: There are too many copies here because we don't fold immediates
50;        through REG_SEQUENCE
51; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
52; TODO: Add VI checks
53; XGCN: s_endpgm
54define amdgpu_kernel void @smrd3(i32 addrspace(4)* %ptr) {
55entry:
56  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296 ; 2 ^ 32
57  %1 = load i32, i32 addrspace(4)* %0
58  store i32 %1, i32 addrspace(1)* undef
59  ret void
60}
61
62; SMRD load with the largest possible immediate offset on VI
63; GCN-LABEL: {{^}}smrd4:
64; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
65; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
66; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
67; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
68define amdgpu_kernel void @smrd4(i32 addrspace(4)* %ptr) {
69entry:
70  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143
71  %1 = load i32, i32 addrspace(4)* %0
72  store i32 %1, i32 addrspace(1)* undef
73  ret void
74}
75
76; SMRD load with an offset greater than the largest possible immediate on VI
77; GCN-LABEL: {{^}}smrd5:
78; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
79; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
80; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
81; GCN: s_endpgm
82define amdgpu_kernel void @smrd5(i32 addrspace(4)* %ptr) {
83entry:
84  %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144
85  %1 = load i32, i32 addrspace(4)* %0
86  store i32 %1, i32 addrspace(1)* undef
87  ret void
88}
89
90