1; RUN: llc < %s -mtriple=amdgcn--amdpal -mcpu=tahiti | FileCheck --check-prefix=PAL --enable-var-scope %s
2
3; PAL-NOT: .AMDGPU.config
4; PAL-LABEL: {{^}}simple:
5define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
6entry:
7  store i32 0, i32 addrspace(1)* %out
8  ret void
9}
10
11; Check code sequence for amdpal use of scratch for alloca. This is the case
12; where the high half of the address comes from s_getpc.
13
14; PAL-LABEL: {{^}}scratch:
15; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
16; PAL: s_mov_b32 s[[GITPTR]], s0
17; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
18; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
19
20define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
21entry:
22  %v = alloca [2 x i32], addrspace(5)
23  %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
24  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
25  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
26  %x = load i32, i32 addrspace(5)* %e
27  store i32 %x, i32 addrspace(5)* %out
28  ret void
29}
30
31; Check code sequence for amdpal use of scratch for alloca. This is the case
32; where the amdgpu-git-ptr-high function attribute gives the high half of the
33; address to use.
34; Looks like you can't do arithmetic on a filecheck variable, so we can't test
35; that the s_movk_i32 is into a reg that is one more than the following
36; s_mov_b32.
37
38; PAL-LABEL: {{^}}scratch2:
39; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
40; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
41; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
42; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
43
44define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
45entry:
46  %v = alloca [2 x i32], addrspace(5)
47  %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
48  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
49  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
50  %x = load i32, i32 addrspace(5)* %e
51  store i32 %x, i32 addrspace(5)* %out
52  ret void
53}
54
55; Check code sequence for amdpal use of scratch for alloca in a compute shader.
56; The scratch descriptor is loaded from offset 0x10 of the GIT, rather than offset
57; 0 in a graphics shader.
58
59; PAL-LABEL: {{^}}scratch2_cs:
60; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
61; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
62; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x10
63; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
64
65define amdgpu_cs void @scratch2_cs(i32 inreg, i32 inreg, i32 inreg, <3 x i32> inreg, i32 inreg, <3 x i32> %coord, <2 x i32> %in, i32 %extra, i32 %idx) #0 {
66entry:
67  %v = alloca [3 x i32], addrspace(5)
68  %v0 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 0
69  %v1 = getelementptr [3 x i32], [3 x i32] addrspace(5)* %v, i32 0, i32 1
70  store i32 %extra, i32 addrspace(5)* %v0
71  %v1a = bitcast i32 addrspace(5)* %v1 to [2 x i32] addrspace(5)*
72  %vv = bitcast [2 x i32] addrspace(5)* %v1a to <2 x i32> addrspace(5)*
73  store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
74  %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v1a, i32 0, i32 %idx
75  %x = load i32, i32 addrspace(5)* %e
76  %xf = bitcast i32 %x to float
77  call void @llvm.amdgcn.buffer.store.f32(float %xf, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
78  ret void
79}
80
81attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
82
83declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1)
84
85
86; Check we have CS_NUM_USED_VGPRS in PAL metadata.
87; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,
88