1; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
3
4; GCN-LABEL: {{^}}main:
5; SI: v_lshl_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
6; VI: v_lshlrev_b32_e64 v{{[0-9]+}}, v{{[0-9]+}}, 1
7define amdgpu_ps float @main(float %arg0, float %arg1) #0 {
8bb:
9  %tmp = fptosi float %arg0 to i32
10  %tmp1 = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 undef, <8 x i32> undef, i32 0, i32 0)
11  %tmp2.f = extractelement <4 x float> %tmp1, i32 0
12  %tmp2 = bitcast float %tmp2.f to i32
13  %tmp3 = and i32 %tmp, 7
14  %tmp4 = shl i32 1, %tmp3
15  %tmp5 = and i32 %tmp2, %tmp4
16  %tmp6 = icmp eq i32 %tmp5, 0
17  %tmp7 = select i1 %tmp6, float 0.000000e+00, float %arg1
18  %tmp8 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp7)
19  %tmp9 = bitcast <2 x half> %tmp8 to float
20  ret float %tmp9
21}
22
23declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
24declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32, i32, <8 x i32>, i32, i32) #2
25
26attributes #0 = { nounwind }
27attributes #1 = { nounwind readnone }
28attributes #2 = { nounwind readonly }
29