1# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck -check-prefix GCN %s
2#
3# GCN: .entry:
4
5--- |
6  ; ModuleID = '<stdin>'
7  source_filename = "llpcPipeline"
8  target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"
9  target triple = "amdgcn--amdpal"
10
11  ; Function Attrs: nounwind readonly
12  declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #0
13
14  ; Function Attrs: nounwind
15  define dllexport amdgpu_ps void @_amdgpu_ps_main() local_unnamed_addr #1 !spirv.ExecutionModel !1 {
16  .entry:
17    %0 = call <2 x float> @llvm.trunc.v2f32(<2 x float> undef)
18    %1 = fptoui <2 x float> %0 to <2 x i32>
19    %2 = lshr <2 x i32> %1, <i32 4, i32 4>
20    %3 = extractelement <2 x i32> %2, i32 0
21    %4 = mul i32 %3, 3
22    %5 = insertelement <4 x i32> undef, i32 %4, i32 1
23    %6 = shufflevector <4 x i32> %5, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
24    %__llpc_global_proxy_r6.8.vec.insert1387 = insertelement <4 x i32> %6, i32 undef, i32 2
25    %__llpc_global_proxy_r6.12.vec.insert1420 = insertelement <4 x i32> %__llpc_global_proxy_r6.8.vec.insert1387, i32 undef, i32 3
26    %__llpc_global_proxy_r6.8.vec.insert1391 = insertelement <4 x i32> %__llpc_global_proxy_r6.12.vec.insert1420, i32 undef, i32 2
27    %__llpc_global_proxy_r4.12.vec.insert1195 = shufflevector <4 x i32> undef, <4 x i32> %__llpc_global_proxy_r6.8.vec.insert1391, <4 x i32> <i32 0, i32 1, i32 2, i32 5>
28    br label %._crit_edge3553
29
30  ._crit_edge3553:                                  ; preds = %._crit_edge3553, %.entry
31    %__llpc_global_proxy_r10.12.vec.extract24363572 = phi i32 [ 0, %.entry ], [ %8, %._crit_edge3553 ]
32    %__llpc_global_proxy_r4.23564 = phi <4 x i32> [ %__llpc_global_proxy_r4.12.vec.insert1195, %.entry ], [ %__llpc_global_proxy_r4.12.vec.insert1200, %._crit_edge3553 ]
33    %__llpc_global_proxy_r4.12.vec.extract = extractelement <4 x i32> %__llpc_global_proxy_r4.23564, i32 3
34    %7 = add i32 %__llpc_global_proxy_r4.12.vec.extract, 1
35    %__llpc_global_proxy_r4.12.vec.insert1200 = insertelement <4 x i32> %__llpc_global_proxy_r4.23564, i32 %7, i32 3
36    %8 = add nuw nsw i32 %__llpc_global_proxy_r10.12.vec.extract24363572, 1
37    %9 = icmp ult i32 %8, 3
38    br i1 %9, label %._crit_edge3553, label %._crit_edge3575, !llvm.loop !2, !amdgpu.uniform !4, !structurizecfg.uniform !4
39
40  ._crit_edge3575:                                  ; preds = %._crit_edge3553
41    br i1 undef, label %._crit_edge3411, label %.lr.ph3410.preheader, !amdgpu.uniform !4
42
43  .lr.ph3410.preheader:                             ; preds = %._crit_edge3575
44    %10 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> undef, i32 %__llpc_global_proxy_r4.12.vec.extract, i32 0, i1 false, i1 false) #6
45    %bc3321.le = bitcast <4 x float> %10 to <4 x i32>
46    %__llpc_global_proxy_r11.12.vec.insert2769.le = shufflevector <4 x i32> undef, <4 x i32> %bc3321.le, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
47    %__llpc_global_proxy_r11.0.vec.insert2624 = insertelement <4 x i32> %__llpc_global_proxy_r11.12.vec.insert2769.le, i32 -1, i32 0
48    br label %.lr.ph3410
49
50  .lr.ph3410:                                       ; preds = %.lr.ph3410, %.lr.ph3410.preheader
51    %__llpc_global_proxy_r11.223394 = phi <4 x i32> [ %11, %.lr.ph3410 ], [ %__llpc_global_proxy_r11.0.vec.insert2624, %.lr.ph3410.preheader ]
52    %11 = shufflevector <4 x i32> <i32 0, i32 0, i32 0, i32 undef>, <4 x i32> %__llpc_global_proxy_r11.223394, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
53    br i1 true, label %.lr.ph3410, label %DummyReturnBlock, !amdgpu.uniform !4, !structurizecfg.uniform !4
54
55  ._crit_edge3411:                                  ; preds = %._crit_edge3575
56    %12 = shufflevector <4 x i32> undef, <4 x i32> %__llpc_global_proxy_r4.12.vec.insert1200, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
57    %__llpc_global_proxy_r4.12.vec.insert1202 = insertelement <4 x i32> %12, i32 undef, i32 3
58    %__llpc_global_proxy_r4.12.vec.insert1208 = insertelement <4 x i32> %__llpc_global_proxy_r4.12.vec.insert1202, i32 undef, i32 3
59    %13 = shufflevector <4 x i32> undef, <4 x i32> %__llpc_global_proxy_r4.12.vec.insert1208, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
60    %__llpc_global_proxy_r4.12.vec.insert1216 = insertelement <4 x i32> %13, i32 undef, i32 3
61    %__llpc_global_proxy_r4.12.vec.insert1232 = insertelement <4 x i32> %__llpc_global_proxy_r4.12.vec.insert1216, i32 undef, i32 3
62    %14 = shufflevector <4 x i32> undef, <4 x i32> %__llpc_global_proxy_r4.12.vec.insert1232, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
63    %15 = shufflevector <4 x i32> %14, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
64    %16 = bitcast <3 x i32> %15 to <3 x float>
65    %17 = fmul reassoc nnan arcp contract <3 x float> %16, zeroinitializer
66    %18 = shufflevector <3 x float> %17, <3 x float> undef, <2 x i32> <i32 0, i32 1>
67    %19 = call <2 x float> @llvm.minnum.v2f32(<2 x float> %18, <2 x float> <float 3.100000e+01, float 3.100000e+01>)
68    %20 = bitcast <2 x float> %19 to <2 x i32>
69    %21 = extractelement <2 x i32> %20, i32 0
70    %22 = insertelement <3 x i32> undef, i32 %21, i32 0
71    %23 = insertelement <3 x i32> %22, i32 undef, i32 1
72    %24 = insertelement <3 x i32> %23, i32 undef, i32 2
73    %25 = bitcast <3 x i32> %24 to <3 x float>
74    %26 = fmul reassoc nnan arcp contract <3 x float> %25, zeroinitializer
75    %27 = fadd reassoc nnan arcp contract <3 x float> zeroinitializer, %26
76    %28 = fmul reassoc nnan arcp contract <3 x float> %27, zeroinitializer
77    %29 = fadd reassoc nnan arcp contract <3 x float> %28, zeroinitializer
78    %30 = bitcast <3 x float> %29 to <3 x i32>
79    %31 = extractelement <3 x i32> %30, i32 0
80    %32 = insertelement <4 x i32> undef, i32 %31, i32 0
81    %33 = insertelement <4 x i32> %32, i32 undef, i32 1
82    %34 = insertelement <4 x i32> %33, i32 undef, i32 2
83    %35 = insertelement <4 x i32> %34, i32 undef, i32 3
84    %36 = shufflevector <4 x i32> %35, <4 x i32> undef, <3 x i32> <i32 0, i32 1, i32 2>
85    %37 = bitcast <3 x i32> %36 to <3 x float>
86    %38 = fmul reassoc nnan arcp contract <3 x float> %37, zeroinitializer
87    %39 = fadd reassoc nnan arcp contract <3 x float> %38, zeroinitializer
88    %40 = extractelement <3 x float> %39, i32 0
89    %41 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %40, float undef) #7
90    call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %41, <2 x half> undef, i1 true, i1 true) #6
91    ret void
92
93  DummyReturnBlock:                                 ; preds = %.lr.ph3410
94    ret void
95  }
96
97  ; Function Attrs: nounwind readnone speculatable
98  declare <2 x float> @llvm.trunc.v2f32(<2 x float>) #2
99
100  ; Function Attrs: nounwind readnone speculatable
101  declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>) #2
102
103  ; Function Attrs: nounwind readnone speculatable
104  declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #2
105
106  ; Function Attrs: nounwind
107  declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #3
108
109  ; Function Attrs: convergent nounwind
110  declare { i1, i64 } @llvm.amdgcn.if(i1) #4
111
112  ; Function Attrs: convergent nounwind
113  declare { i1, i64 } @llvm.amdgcn.else(i64) #4
114
115  ; Function Attrs: convergent nounwind readnone
116  declare i64 @llvm.amdgcn.break(i64) #5
117
118  ; Function Attrs: convergent nounwind readnone
119  declare i64 @llvm.amdgcn.if.break(i1, i64) #5
120
121  ; Function Attrs: convergent nounwind readnone
122  declare i64 @llvm.amdgcn.else.break(i64, i64) #5
123
124  ; Function Attrs: convergent nounwind
125  declare i1 @llvm.amdgcn.loop(i64) #4
126
127  ; Function Attrs: convergent nounwind
128  declare void @llvm.amdgcn.end.cf(i64) #4
129
130  ; Function Attrs: nounwind
131  declare void @llvm.stackprotector(i8*, i8**) #6
132
133  attributes #0 = { nounwind readonly "target-cpu"="gfx900" }
134  attributes #1 = { nounwind "InitialPSInputAddr"="3841" "target-cpu"="gfx900" }
135  attributes #2 = { nounwind readnone speculatable "target-cpu"="gfx900" }
136  attributes #3 = { nounwind "target-cpu"="gfx900" }
137  attributes #4 = { convergent nounwind }
138  attributes #5 = { convergent nounwind readnone }
139  attributes #6 = { nounwind }
140  attributes #7 = { nounwind readnone speculatable }
141
142  !amdgpu.pal.metadata = !{!0}
143
144  !0 = !{i32 268435482, i32 7, i32 268435488, i32 -1, i32 268435480, i32 916933962, i32 268435481, i32 -1162810017, i32 268435538, i32 4096, i32 268435539, i32 8192, i32 11338, i32 53215232, i32 11339, i32 20, i32 41411, i32 4, i32 41393, i32 8, i32 41479, i32 0, i32 41476, i32 17301504, i32 41478, i32 1087, i32 41721, i32 45, i32 41633, i32 0, i32 41645, i32 0, i32 268435528, i32 0, i32 268435493, i32 0, i32 268435500, i32 0, i32 268435507, i32 256, i32 268435514, i32 104, i32 268435536, i32 0, i32 11274, i32 2883584, i32 11275, i32 6, i32 41412, i32 0, i32 41413, i32 4, i32 41400, i32 16908288, i32 41398, i32 5, i32 41395, i32 0, i32 41396, i32 0, i32 41397, i32 0, i32 41619, i32 100860300, i32 41475, i32 6160, i32 41103, i32 15, i32 268435485, i32 0, i32 268435529, i32 0, i32 268435494, i32 0, i32 268435501, i32 0, i32 268435508, i32 256, i32 268435515, i32 104, i32 41720, i32 0, i32 41744, i32 0, i32 41747, i32 2097152, i32 41685, i32 65536, i32 268435460, i32 1376215782, i32 268435461, i32 835526634, i32 268435476, i32 -918515376, i32 268435477, i32 679325817, i32 268435532, i32 7, i32 49752, i32 127, i32 11348, i32 268435459, i32 11349, i32 268435460, i32 11340, i32 268435456, i32 11342, i32 0, i32 11343, i32 1, i32 11344, i32 2, i32 11345, i32 3, i32 11346, i32 4, i32 11347, i32 6, i32 41361, i32 0, i32 41362, i32 1, i32 41363, i32 2, i32 41364, i32 3, i32 41365, i32 4, i32 11276, i32 268435456, i32 11278, i32 5}
145  !1 = !{i32 4}
146  !2 = distinct !{!2, !3}
147  !3 = !{!"llvm.loop.unroll.count", i32 32}
148  !4 = !{}
149
150...
151---
152name:            _amdgpu_ps_main
153alignment:       0
154exposesReturnsTwice: false
155legalized:       false
156regBankSelected: false
157selected:        false
158failedISel:      false
159tracksRegLiveness: true
160registers:
161  - { id: 0, class: sreg_128, preferred-register: '' }
162  - { id: 1, class: sreg_32_xm0, preferred-register: '%5' }
163  - { id: 2, class: sreg_128, preferred-register: '' }
164  - { id: 3, class: sreg_32_xm0, preferred-register: '' }
165  - { id: 4, class: sreg_128, preferred-register: '' }
166  - { id: 5, class: sreg_32_xm0, preferred-register: '%1' }
167  - { id: 6, class: sreg_128, preferred-register: '' }
168  - { id: 7, class: sreg_128, preferred-register: '' }
169  - { id: 8, class: sreg_128, preferred-register: '' }
170  - { id: 9, class: sreg_32_xm0, preferred-register: '' }
171  - { id: 10, class: vgpr_32, preferred-register: '' }
172  - { id: 11, class: vgpr_32, preferred-register: '' }
173  - { id: 12, class: vgpr_32, preferred-register: '' }
174  - { id: 13, class: sreg_32_xm0, preferred-register: '' }
175  - { id: 14, class: sreg_32_xm0, preferred-register: '' }
176  - { id: 15, class: sreg_32, preferred-register: '' }
177  - { id: 16, class: sreg_32_xm0, preferred-register: '' }
178  - { id: 17, class: sreg_32_xm0, preferred-register: '' }
179  - { id: 18, class: sreg_128, preferred-register: '' }
180  - { id: 19, class: sreg_32_xm0, preferred-register: '' }
181  - { id: 20, class: sreg_32_xm0, preferred-register: '' }
182  - { id: 21, class: sreg_32_xm0, preferred-register: '' }
183  - { id: 22, class: vreg_128, preferred-register: '' }
184  - { id: 23, class: vgpr_32, preferred-register: '' }
185  - { id: 24, class: sreg_128, preferred-register: '' }
186  - { id: 25, class: sreg_32_xm0, preferred-register: '' }
187  - { id: 26, class: sreg_32_xm0, preferred-register: '' }
188  - { id: 27, class: sreg_128, preferred-register: '' }
189  - { id: 28, class: sreg_32_xm0, preferred-register: '' }
190  - { id: 29, class: sreg_32_xm0, preferred-register: '' }
191  - { id: 30, class: sreg_32_xm0, preferred-register: '' }
192  - { id: 31, class: sreg_32_xm0, preferred-register: '' }
193  - { id: 32, class: sreg_32_xm0, preferred-register: '' }
194  - { id: 33, class: sreg_32_xm0, preferred-register: '' }
195  - { id: 34, class: sreg_128, preferred-register: '' }
196  - { id: 35, class: sreg_64, preferred-register: '' }
197  - { id: 36, class: sreg_64, preferred-register: '' }
198  - { id: 37, class: vgpr_32, preferred-register: '' }
199  - { id: 38, class: vgpr_32, preferred-register: '' }
200  - { id: 39, class: vgpr_32, preferred-register: '' }
201  - { id: 40, class: vgpr_32, preferred-register: '' }
202  - { id: 41, class: vgpr_32, preferred-register: '' }
203  - { id: 42, class: vgpr_32, preferred-register: '' }
204  - { id: 43, class: vgpr_32, preferred-register: '' }
205  - { id: 44, class: vgpr_32, preferred-register: '' }
206  - { id: 45, class: vgpr_32, preferred-register: '' }
207  - { id: 46, class: vgpr_32, preferred-register: '' }
208  - { id: 47, class: vgpr_32, preferred-register: '' }
209  - { id: 48, class: vgpr_32, preferred-register: '' }
210  - { id: 49, class: vgpr_32, preferred-register: '' }
211  - { id: 50, class: vgpr_32, preferred-register: '' }
212  - { id: 51, class: vgpr_32, preferred-register: '' }
213  - { id: 52, class: vreg_128, preferred-register: '' }
214  - { id: 53, class: vreg_128, preferred-register: '' }
215  - { id: 54, class: vreg_128, preferred-register: '' }
216  - { id: 55, class: vreg_128, preferred-register: '' }
217  - { id: 56, class: vgpr_32, preferred-register: '' }
218  - { id: 57, class: vgpr_32, preferred-register: '' }
219  - { id: 58, class: vgpr_32, preferred-register: '' }
220  - { id: 59, class: vreg_128, preferred-register: '' }
221  - { id: 60, class: vgpr_32, preferred-register: '' }
222  - { id: 61, class: vgpr_32, preferred-register: '' }
223  - { id: 62, class: vgpr_32, preferred-register: '' }
224  - { id: 63, class: vreg_128, preferred-register: '' }
225  - { id: 64, class: vreg_128, preferred-register: '' }
226  - { id: 65, class: vgpr_32, preferred-register: '' }
227  - { id: 66, class: vreg_128, preferred-register: '' }
228  - { id: 67, class: vgpr_32, preferred-register: '' }
229  - { id: 68, class: vgpr_32, preferred-register: '' }
230  - { id: 69, class: vgpr_32, preferred-register: '' }
231  - { id: 70, class: sreg_32_xm0, preferred-register: '' }
232  - { id: 71, class: vreg_128, preferred-register: '' }
233liveins:
234frameInfo:
235  isFrameAddressTaken: false
236  isReturnAddressTaken: false
237  hasStackMap:     false
238  hasPatchPoint:   false
239  stackSize:       0
240  offsetAdjustment: 0
241  maxAlignment:    0
242  adjustsStack:    false
243  hasCalls:        false
244  stackProtector:  ''
245  maxCallFrameSize: 4294967295
246  hasOpaqueSPAdjustment: false
247  hasVAStart:      false
248  hasMustTailInVarArgFunc: false
249  localFrameSize:  0
250  savePoint:       ''
251  restorePoint:    ''
252fixedStack:
253stack:
254constants:
255body:             |
256  bb.0..entry:
257    successors: %bb.1(0x80000000)
258
259    %10:vgpr_32 = V_TRUNC_F32_e32 undef %11:vgpr_32, implicit $exec
260    %12:vgpr_32 = V_CVT_U32_F32_e32 killed %10, implicit $exec
261    %50:vgpr_32 = V_LSHRREV_B32_e32 4, killed %12, implicit $exec
262    %51:vgpr_32 = V_MUL_LO_I32 killed %50, 3, implicit $exec
263    undef %52.sub0:vreg_128 = COPY %51
264    %52.sub3:vreg_128 = COPY %51
265    %9:sreg_32_xm0 = S_MOV_B32 0
266    %70:sreg_32_xm0 = COPY killed %9
267    %71:vreg_128 = COPY killed %52
268
269  bb.1.._crit_edge3553:
270    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
271
272    %53:vreg_128 = COPY killed %71
273    %1:sreg_32_xm0 = COPY killed %70
274    %57:vgpr_32 = V_ADD_U32_e32 target-flags(amdgpu-rel32-lo) 1, %53.sub3, implicit $exec
275    %55:vreg_128 = COPY %53
276    %55.sub3:vreg_128 = COPY killed %57
277    %5:sreg_32_xm0 = S_ADD_I32 killed %1, 1, implicit-def dead $scc
278    S_CMP_LT_U32 %5, 3, implicit-def $scc
279    %54:vreg_128 = COPY %55
280    %70:sreg_32_xm0 = COPY killed %5
281    %71:vreg_128 = COPY killed %54
282    S_CBRANCH_SCC1 %bb.1, implicit killed $scc
283    S_BRANCH %bb.2
284
285  bb.2.._crit_edge3575:
286    successors: %bb.5(0x40000000), %bb.3(0x40000000)
287
288    S_CBRANCH_SCC1 %bb.5, implicit undef $scc
289    S_BRANCH %bb.3
290
291  bb.3..lr.ph3410.preheader:
292    successors: %bb.4(0x80000000)
293
294    dead %22:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_IDXEN killed %53.sub3, undef %24:sreg_128, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load 16 from constant-pool, align 1, addrspace 4)
295    dead %60:vgpr_32 = V_MOV_B32_e32 -1, implicit $exec
296    %36:sreg_64 = S_AND_B64 $exec, -1, implicit-def dead $scc
297    dead %67:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
298
299  bb.4..lr.ph3410:
300    successors: %bb.4(0x7c000000), %bb.6(0x04000000)
301
302    $vcc = COPY %36
303    S_CBRANCH_VCCNZ %bb.4, implicit killed $vcc
304    S_BRANCH %bb.6
305
306  bb.5.._crit_edge3411:
307    %39:vgpr_32 = V_MUL_F32_e32 target-flags(amdgpu-gotprel) 0, killed %55.sub0, implicit $exec
308    %41:vgpr_32 = V_MIN_F32_e32 1106771968, killed %39, implicit $exec
309    %42:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %41, 0, 0, 0, 0, 0, 0, implicit $exec
310    %43:vgpr_32 = nnan arcp contract reassoc V_MAD_F32 0, killed %42, 0, 0, 0, 0, 0, 0, implicit $exec
311    %44:vgpr_32 = V_MAD_F32 0, killed %43, 0, 0, 0, 0, 0, 0, implicit $exec
312    %45:vgpr_32 = V_CVT_PKRTZ_F16_F32_e64 0, killed %44, 0, undef %46:vgpr_32, 0, implicit $exec
313    EXP_DONE 0, killed %45, undef %47:vgpr_32, undef %48:vgpr_32, undef %49:vgpr_32, -1, -1, 15, implicit $exec
314    S_ENDPGM
315
316  bb.6.DummyReturnBlock:
317    S_ENDPGM
318
319...
320