1; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | FileCheck --check-prefix=HSA %s
2; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
3; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo  | FileCheck --check-prefix=HSA %s
4; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
5; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj | llvm-readobj -symbols -s -sd | FileCheck --check-prefix=ELF %s
6; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri | llvm-readobj -symbols -s -sd | FileCheck %s --check-prefix=ELF
7
8; The SHT_NOTE section contains the output from the .hsa_code_object_*
9; directives.
10
11; ELF: Section {
12; ELF: Name: .text
13; ELF: Type: SHT_PROGBITS (0x1)
14; ELF: Flags [ (0x6)
15; ELF: SHF_ALLOC (0x2)
16; ELF: SHF_EXECINSTR (0x4)
17; ELF: }
18
19; ELF: SHT_NOTE
20; ELF: Flags [ (0x2)
21; ELF: SHF_ALLOC (0x2)
22; ELF: ]
23; ELF: SectionData (
24; ELF: 0000: 04000000 08000000 01000000 414D4400
25; ELF: 0010: 02000000 01000000 04000000 1B000000
26; ELF: 0020: 03000000 414D4400 04000700 07000000
27; ELF: 0030: 00000000 00000000 414D4400 414D4447
28; ELF: 0040: 50550000
29; ELF: )
30
31; ELF: Symbol {
32; ELF: Name: simple
33; ELF: Size: 288
34; ELF: Type: AMDGPU_HSA_KERNEL (0xA)
35; ELF: }
36
37; HSA-NOT: .AMDGPU.config
38; HSA: .text
39; HSA: .hsa_code_object_version 2,1
40; HSA-CI: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
41; HSA-VI: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
42
43; HSA-LABEL: .amdgpu_hsa_kernel simple
44; HSA: {{^}}simple:
45; HSA: .amd_kernel_code_t
46; HSA: enable_sgpr_private_segment_buffer = 1
47; HSA: enable_sgpr_kernarg_segment_ptr = 1
48; HSA: wavefront_size = 6
49; HSA: call_convention = -1
50; HSA: .end_amd_kernel_code_t
51; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
52
53; Make sure we are setting the ATC bit:
54; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
55; On VI+ we also need to set MTYPE = 2
56; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
57; Make sure we generate flat store for HSA
58; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
59
60; HSA: .Lfunc_end0:
61; HSA: .size   simple, .Lfunc_end0-simple
62
63define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
64entry:
65  store i32 0, i32 addrspace(1)* %out
66  ret void
67}
68
69; HSA-LABEL: .amdgpu_hsa_kernel simple_no_kernargs
70; HSA: enable_sgpr_kernarg_segment_ptr = 0
71define amdgpu_kernel void @simple_no_kernargs() {
72entry:
73  store volatile i32 0, i32 addrspace(1)* undef
74  ret void
75}
76