1;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=SICI 2;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -check-prefix=VI 3 4;CHECK-LABEL: {{^}}test1: 5;CHECK-NOT: s_waitcnt 6;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc 7;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc 8;CHECK: s_waitcnt vmcnt(0) 9;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc 10;CHECK: s_waitcnt vmcnt(0) 11;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc 12;CHECK: s_waitcnt vmcnt(0) 13;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc 14;CHECK: s_waitcnt vmcnt(0) 15;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc 16;CHECK-DAG: s_waitcnt vmcnt(0) 17;SICI: buffer_atomic_swap v0, v1, s[0:3], 0 offen glc 18;VI: buffer_atomic_swap v0, off, s[0:3], [[SOFS]] offset:4 glc 19;CHECK: s_waitcnt vmcnt(0) 20;CHECK: buffer_atomic_swap v0, off, s[0:3], 0{{$}} 21define amdgpu_ps float @test1(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex, i32 %voffset) { 22main_body: 23 %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0) 24 %o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 25 %o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) 26 %o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) 27 %ofs.5 = add i32 %voffset, 42 28 %o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) 29 %o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) 30 %unused = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0) 31 %out = bitcast i32 %o6 to float 32 ret float %out 33} 34 35;CHECK-LABEL: {{^}}test2: 36;CHECK-NOT: s_waitcnt 37;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc 38;CHECK: s_waitcnt vmcnt(0) 39;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc 40;CHECK: s_waitcnt vmcnt(0) 41;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc 42;CHECK: s_waitcnt vmcnt(0) 43;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc 44;CHECK: s_waitcnt vmcnt(0) 45;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc 46;CHECK: s_waitcnt vmcnt(0) 47;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc 48;CHECK: s_waitcnt vmcnt(0) 49;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc 50;CHECK: s_waitcnt vmcnt(0) 51;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc 52;CHECK: s_waitcnt vmcnt(0) 53;CHECK: buffer_atomic_xor v0, v1, s[0:3], 0 idxen glc 54define amdgpu_ps float @test2(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) { 55main_body: 56 %t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 57 %t2 = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %t1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 58 %t3 = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %t2, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 59 %t4 = call i32 @llvm.amdgcn.buffer.atomic.umin(i32 %t3, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 60 %t5 = call i32 @llvm.amdgcn.buffer.atomic.smax(i32 %t4, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 61 %t6 = call i32 @llvm.amdgcn.buffer.atomic.umax(i32 %t5, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 62 %t7 = call i32 @llvm.amdgcn.buffer.atomic.and(i32 %t6, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 63 %t8 = call i32 @llvm.amdgcn.buffer.atomic.or(i32 %t7, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 64 %t9 = call i32 @llvm.amdgcn.buffer.atomic.xor(i32 %t8, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 65 %out = bitcast i32 %t9 to float 66 ret float %out 67} 68 69; Ideally, we would teach tablegen & friends that cmpswap only modifies the 70; first vgpr. Since we don't do that yet, the register allocator will have to 71; create copies which we don't bother to track here. 72; 73;CHECK-LABEL: {{^}}test3: 74;CHECK-NOT: s_waitcnt 75;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], 0 glc 76;CHECK: s_waitcnt vmcnt(0) 77;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc 78;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v2, s[0:3], 0 idxen glc 79;CHECK: s_waitcnt vmcnt(0) 80;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen glc 81;CHECK: s_waitcnt vmcnt(0) 82;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v[2:3], s[0:3], 0 idxen offen glc 83;CHECK: s_waitcnt vmcnt(0) 84;CHECK: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, v3, s[0:3], 0 offen offset:44 glc 85;CHECK-DAG: s_waitcnt vmcnt(0) 86;SICI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, s[0:3], 0 offen glc 87;VI: buffer_atomic_cmpswap {{v\[[0-9]+:[0-9]+\]}}, off, s[0:3], [[SOFS]] offset:4 glc 88define amdgpu_ps float @test3(<4 x i32> inreg %rsrc, i32 %data, i32 %cmp, i32 %vindex, i32 %voffset) { 89main_body: 90 %o1 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %data, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0) 91 %o2 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o1, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0) 92 %o3 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o2, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0) 93 %o4 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o3, i32 %cmp, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i1 0) 94 %ofs.5 = add i32 %voffset, 44 95 %o5 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o4, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0) 96 %o6 = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o5, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 8192, i1 0) 97 98; Detecting the no-return variant doesn't work right now because of how the 99; intrinsic is replaced by an instruction that feeds into an EXTRACT_SUBREG. 100; Since there probably isn't a reasonable use-case of cmpswap that discards 101; the return value, that seems okay. 102; 103; %unused = call i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32 %o6, i32 %cmp, <4 x i32> %rsrc, i32 0, i32 0, i1 0) 104 %out = bitcast i32 %o6 to float 105 ret float %out 106} 107 108;CHECK-LABEL: {{^}}test4: 109;CHECK: buffer_atomic_add v0, 110define amdgpu_ps float @test4() { 111main_body: 112 %v = call i32 @llvm.amdgcn.buffer.atomic.add(i32 1, <4 x i32> undef, i32 0, i32 4, i1 false) 113 %v.float = bitcast i32 %v to float 114 ret float %v.float 115} 116 117declare i32 @llvm.amdgcn.buffer.atomic.swap(i32, <4 x i32>, i32, i32, i1) #0 118declare i32 @llvm.amdgcn.buffer.atomic.add(i32, <4 x i32>, i32, i32, i1) #0 119declare i32 @llvm.amdgcn.buffer.atomic.sub(i32, <4 x i32>, i32, i32, i1) #0 120declare i32 @llvm.amdgcn.buffer.atomic.smin(i32, <4 x i32>, i32, i32, i1) #0 121declare i32 @llvm.amdgcn.buffer.atomic.umin(i32, <4 x i32>, i32, i32, i1) #0 122declare i32 @llvm.amdgcn.buffer.atomic.smax(i32, <4 x i32>, i32, i32, i1) #0 123declare i32 @llvm.amdgcn.buffer.atomic.umax(i32, <4 x i32>, i32, i32, i1) #0 124declare i32 @llvm.amdgcn.buffer.atomic.and(i32, <4 x i32>, i32, i32, i1) #0 125declare i32 @llvm.amdgcn.buffer.atomic.or(i32, <4 x i32>, i32, i32, i1) #0 126declare i32 @llvm.amdgcn.buffer.atomic.xor(i32, <4 x i32>, i32, i32, i1) #0 127declare i32 @llvm.amdgcn.buffer.atomic.cmpswap(i32, i32, <4 x i32>, i32, i32, i1) #0 128 129attributes #0 = { nounwind } 130