1# RUN: llc -march=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
2
3# GCN:    bb.0.entry:
4# GCN:      SI_INIT_M0 -1
5# GCN-NEXT: DS_WRITE_B32
6# GCN-NEXT: DS_WRITE_B32
7# GCN-NEXT: SI_INIT_M0 65536
8# GCN-NEXT: DS_WRITE_B32
9# GCN-NEXT: DS_WRITE_B32
10# GCN-NEXT: SI_INIT_M0 -1
11# GCN-NEXT: DS_WRITE_B32
12# GCN-NEXT: SI_INIT_M0 65536
13# GCN-NEXT: DS_WRITE_B32
14
15# GCN:    bb.1:
16# GCN:      SI_INIT_M0 -1
17# GCN-NEXT: DS_WRITE_B32
18# GCN-NEXT: DS_WRITE_B32
19
20# GCN:    bb.2:
21# GCN:      SI_INIT_M0 65536
22# GCN-NEXT: DS_WRITE_B32
23
24# GCN:    bb.3:
25# GCN:      SI_INIT_M0 3
26
27# GCN:    bb.4:
28# GCN-NOT:  SI_INIT_M0
29# GCN:      DS_WRITE_B32
30# GCN-NEXT: SI_INIT_M0 4
31# GCN-NEXT: DS_WRITE_B32
32
33# GCN:    bb.5:
34# GCN-NOT: SI_INIT_M0
35# GCN:     DS_WRITE_B32
36# GCN-NEXT: SI_INIT_M0 4
37# GCN-NEXT: DS_WRITE_B32
38
39# GCN:    bb.6:
40# GCN:      SI_INIT_M0 -1,
41# GCN-NEXT: DS_WRITE_B32
42# GCN:      SI_INIT_M0 %2
43# GCN-NEXT: DS_WRITE_B32
44# GCN-NEXT: SI_INIT_M0 %2
45# GCN-NEXT: DS_WRITE_B32
46# GCN-NEXT: SI_INIT_M0 -1
47# GCN-NEXT: DS_WRITE_B32
48
49---
50name:            test
51alignment:       0
52exposesReturnsTwice: false
53legalized:       false
54regBankSelected: false
55selected:        false
56tracksRegLiveness: true
57registers:
58  - { id: 0, class: vgpr_32 }
59  - { id: 1, class: vgpr_32 }
60  - { id: 2, class: sreg_32_xm0 }
61body:             |
62  bb.0.entry:
63    successors: %bb.1, %bb.2
64
65    %0 = IMPLICIT_DEF
66    %1 = IMPLICIT_DEF
67    SI_INIT_M0 -1, implicit-def $m0
68    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
69    SI_INIT_M0 -1, implicit-def $m0
70    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
71    SI_INIT_M0 65536, implicit-def $m0
72    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
73    SI_INIT_M0 65536, implicit-def $m0
74    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
75    SI_INIT_M0 -1, implicit-def $m0
76    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
77    SI_INIT_M0 65536, implicit-def $m0
78    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
79    S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
80    S_BRANCH %bb.2
81
82  bb.1:
83    successors: %bb.2
84    SI_INIT_M0 -1, implicit-def $m0
85    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
86    SI_INIT_M0 -1, implicit-def $m0
87    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
88    S_BRANCH %bb.2
89
90  bb.2:
91    successors: %bb.3
92    SI_INIT_M0 65536, implicit-def $m0
93    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
94    S_BRANCH %bb.3
95
96  bb.3:
97    successors: %bb.4, %bb.5
98    S_CBRANCH_VCCZ %bb.4, implicit undef $vcc
99    S_BRANCH %bb.5
100
101  bb.4:
102    successors: %bb.6
103    SI_INIT_M0 3, implicit-def $m0
104    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
105    SI_INIT_M0 4, implicit-def $m0
106    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
107    S_BRANCH %bb.6
108
109  bb.5:
110    successors: %bb.6
111    SI_INIT_M0 3, implicit-def $m0
112    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
113    SI_INIT_M0 4, implicit-def $m0
114    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
115    S_BRANCH %bb.6
116
117  bb.6:
118    successors: %bb.0.entry, %bb.6
119    SI_INIT_M0 -1, implicit-def $m0
120    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
121    %2 = IMPLICIT_DEF
122    SI_INIT_M0 %2, implicit-def $m0
123    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
124    SI_INIT_M0 %2, implicit-def $m0
125    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
126    SI_INIT_M0 -1, implicit-def $m0
127    DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
128    S_CBRANCH_VCCZ %bb.6, implicit undef $vcc
129    S_BRANCH %bb.0.entry
130
131...
132