1; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
2
3; Test that buffer_load_format with VGPR resource descriptor is properly
4; legalized.
5
6; CHECK-LABEL: {{^}}test_none:
7; CHECK: buffer_load_format_x v0, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
8define amdgpu_vs float @test_none(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
9main_body:
10  %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
11  %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
12  %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i1 0, i1 0)
13  ret float %tmp7
14}
15
16; CHECK-LABEL: {{^}}test_idxen:
17; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen{{$}}
18define amdgpu_vs float @test_idxen(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
19main_body:
20  %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
21  %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
22  %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i1 0, i1 0)
23  ret float %tmp7
24}
25
26; CHECK-LABEL: {{^}}test_offen:
27; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
28define amdgpu_vs float @test_offen(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
29main_body:
30  %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
31  %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
32  %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 undef, i1 0, i1 0)
33  ret float %tmp7
34}
35
36; CHECK-LABEL: {{^}}test_both:
37; CHECK: buffer_load_format_x v0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen{{$}}
38define amdgpu_vs float @test_both(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
39main_body:
40  %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
41  %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
42  %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i1 0, i1 0)
43  ret float %tmp7
44}
45
46declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) nounwind readonly
47
48attributes #0 = { nounwind readnone }
49