1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI -check-prefix=OPT %s
3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI -check-prefix=OPT %s
4; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=OPTNONE %s
5
6; There are no stack objects, but still a private memory access. The
7; private access regiters need to be correctly initialized anyway, and
8; shifted down to the end of the used registers.
9
10; GCN-LABEL: {{^}}store_to_undef:
11; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
12; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
13; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
14; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
15
16; -O0 should assume spilling, so the input scratch resource descriptor
17; -should be used directly without any copies.
18
19; OPTNONE-NOT: s_mov_b32
20; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}}
21define amdgpu_kernel void @store_to_undef() #0 {
22  store volatile i32 0, i32 addrspace(5)* undef
23  ret void
24}
25
26; GCN-LABEL: {{^}}store_to_inttoptr:
27; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
28; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
29; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
30; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
31define amdgpu_kernel void @store_to_inttoptr() #0 {
32 store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
33 ret void
34}
35
36; GCN-LABEL: {{^}}load_from_undef:
37; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
38; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
39; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
40; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
41define amdgpu_kernel void @load_from_undef() #0 {
42  %ld = load volatile i32, i32 addrspace(5)* undef
43  ret void
44}
45
46; GCN-LABEL: {{^}}load_from_inttoptr:
47; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
48; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
49; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
50; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
51define amdgpu_kernel void @load_from_inttoptr() #0 {
52  %ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
53  ret void
54}
55
56attributes #0 = { nounwind }
57