1; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9,GCN %s
2; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,CIVI,GCN %s
3; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CI,CIVI,GCN %s
4
5; GCN-LABEL: {{^}}s_abs_v2i16:
6; GFX9: s_load_dword [[VAL:s[0-9]+]]
7; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
8; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
9; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[MAX]], 2
10
11; CIVI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
12; CIVI: s_sub_i32
13; CIVI: s_sub_i32
14; CIVI: s_max_i32
15; CIVI: s_max_i32
16; CIVI: s_add_i32
17; CIVI: s_add_i32
18; CIVI: s_and_b32
19; CIVI: s_or_b32
20define amdgpu_kernel void @s_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
21  %neg = sub <2 x i16> zeroinitializer, %val
22  %cond = icmp sgt <2 x i16> %val, %neg
23  %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
24  %res2 = add <2 x i16> %res, <i16 2, i16 2>
25  store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
26  ret void
27}
28
29; GCN-LABEL: {{^}}v_abs_v2i16:
30; GFX9: global_load_dword [[VAL:v[0-9]+]]
31; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
32; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
33; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[MAX]], 2
34
35; VI: v_mov_b32_e32 [[TWO:v[0-9]+]], 2
36; VI: v_lshrrev_b32_e32 v{{[0-9]+}}, 16,
37; VI: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
38; VI: v_sub_u16_e32 v{{[0-9]+}}, 0, v{{[0-9]+}}
39; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
40; VI: v_max_i16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
41; VI: v_add_u16_e32 v{{[0-9]+}}, 2, v{{[0-9]+}}
42; VI: v_add_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, [[TWO]]  dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
43; VI-NOT: v_and_b32
44; VI: v_or_b32_e32
45
46; CI: buffer_load_dword v
47; CI: v_lshrrev_b32_e32
48; CI: v_sub_i32_e32
49; CI: v_bfe_i32
50; CI: v_bfe_i32
51; CI: v_max_i32
52; CI: v_max_i32
53; CI: v_add_i32
54; CI: v_add_i32
55; CI: v_or_b32
56define amdgpu_kernel void @v_abs_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
57  %tid = call i32 @llvm.amdgcn.workitem.id.x()
58  %gep.in = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %src, i32 %tid
59  %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
60  %val = load <2 x i16>, <2 x i16> addrspace(1)* %gep.in, align 4
61  %neg = sub <2 x i16> zeroinitializer, %val
62  %cond = icmp sgt <2 x i16> %val, %neg
63  %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
64  %res2 = add <2 x i16> %res, <i16 2, i16 2>
65  store <2 x i16> %res2, <2 x i16> addrspace(1)* %gep.out, align 4
66  ret void
67}
68
69; GCN-LABEL: {{^}}s_abs_v2i16_2:
70; GFX9: s_load_dword [[VAL:s[0-9]+]]
71; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
72; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
73; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[MAX]], 2
74define amdgpu_kernel void @s_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> %val) #0 {
75  %z0 = insertelement <2 x i16> undef, i16 0, i16 0
76  %z1 = insertelement <2 x i16> %z0, i16 0, i16 1
77  %t0 = insertelement <2 x i16> undef, i16 2, i16 0
78  %t1 = insertelement <2 x i16> %t0, i16 2, i16 1
79  %neg = sub <2 x i16> %z1, %val
80  %cond = icmp sgt <2 x i16> %val, %neg
81  %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
82  %res2 = add <2 x i16> %res, %t1
83  store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
84  ret void
85}
86
87; GCN-LABEL: {{^}}v_abs_v2i16_2:
88; GFX9: buffer_load_dword [[VAL:v[0-9]+]]
89; GFX9: v_pk_sub_i16 [[SUB:v[0-9]+]], 0, [[VAL]]
90; GFX9: v_pk_max_i16 [[MAX:v[0-9]+]], [[VAL]], [[SUB]]
91; GFX9: v_pk_add_u16 [[ADD:v[0-9]+]], [[MAX]], 2
92define amdgpu_kernel void @v_abs_v2i16_2(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %src) #0 {
93  %z0 = insertelement <2 x i16> undef, i16 0, i16 0
94  %z1 = insertelement <2 x i16> %z0, i16 0, i16 1
95  %t0 = insertelement <2 x i16> undef, i16 2, i16 0
96  %t1 = insertelement <2 x i16> %t0, i16 2, i16 1
97  %val = load <2 x i16>, <2 x i16> addrspace(1)* %src, align 4
98  %neg = sub <2 x i16> %z1, %val
99  %cond = icmp sgt <2 x i16> %val, %neg
100  %res = select <2 x i1> %cond, <2 x i16> %val, <2 x i16> %neg
101  %res2 = add <2 x i16> %res, %t1
102  store <2 x i16> %res2, <2 x i16> addrspace(1)* %out, align 4
103  ret void
104}
105
106; GCN-LABEL: {{^}}s_abs_v4i16:
107; GFX9: s_load_dwordx2 s{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}, s[0:1], 0x2c
108; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, s[[VAL0]]
109; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, s[[VAL1]]
110; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], s[[VAL0]], [[SUB0]]
111; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], s[[VAL1]], [[SUB1]]
112; GFX9-DAG: v_pk_add_u16 [[ADD0:v[0-9]+]], [[MAX0]], 2 op_sel_hi:[1,0]
113; GFX9-DAG: v_pk_add_u16 [[ADD1:v[0-9]+]], [[MAX1]], 2 op_sel_hi:[1,0]
114define amdgpu_kernel void @s_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> %val) #0 {
115  %z0 = insertelement <4 x i16> undef, i16 0, i16 0
116  %z1 = insertelement <4 x i16> %z0, i16 0, i16 1
117  %z2 = insertelement <4 x i16> %z1, i16 0, i16 2
118  %z3 = insertelement <4 x i16> %z2, i16 0, i16 3
119  %t0 = insertelement <4 x i16> undef, i16 2, i16 0
120  %t1 = insertelement <4 x i16> %t0, i16 2, i16 1
121  %t2 = insertelement <4 x i16> %t1, i16 2, i16 2
122  %t3 = insertelement <4 x i16> %t2, i16 2, i16 3
123  %neg = sub <4 x i16> %z3, %val
124  %cond = icmp sgt <4 x i16> %val, %neg
125  %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
126  %res2 = add <4 x i16> %res, %t3
127  store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
128  ret void
129}
130
131; GCN-LABEL: {{^}}v_abs_v4i16:
132; GFX9: buffer_load_dwordx2 v{{\[}}[[VAL0:[0-9]+]]:[[VAL1:[0-9]+]]{{\]}}
133
134; GFX9-DAG: v_pk_sub_i16 [[SUB0:v[0-9]+]], 0, v[[VAL0]]
135; GFX9-DAG: v_pk_max_i16 [[MAX0:v[0-9]+]], v[[VAL0]], [[SUB0]]
136; GFX9-DAG: v_pk_add_u16 [[ADD0:v[0-9]+]], [[MAX0]], 2
137
138; GFX9-DAG: v_pk_sub_i16 [[SUB1:v[0-9]+]], 0, v[[VAL1]]
139; GFX9-DAG: v_pk_max_i16 [[MAX1:v[0-9]+]], v[[VAL1]], [[SUB1]]
140; GFX9-DAG: v_pk_add_u16 [[ADD1:v[0-9]+]], [[MAX1]], 2
141define amdgpu_kernel void @v_abs_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %src) #0 {
142  %z0 = insertelement <4 x i16> undef, i16 0, i16 0
143  %z1 = insertelement <4 x i16> %z0, i16 0, i16 1
144  %z2 = insertelement <4 x i16> %z1, i16 0, i16 2
145  %z3 = insertelement <4 x i16> %z2, i16 0, i16 3
146  %t0 = insertelement <4 x i16> undef, i16 2, i16 0
147  %t1 = insertelement <4 x i16> %t0, i16 2, i16 1
148  %t2 = insertelement <4 x i16> %t1, i16 2, i16 2
149  %t3 = insertelement <4 x i16> %t2, i16 2, i16 3
150  %val = load <4 x i16>, <4 x i16> addrspace(1)* %src, align 4
151  %neg = sub <4 x i16> %z3, %val
152  %cond = icmp sgt <4 x i16> %val, %neg
153  %res = select <4 x i1> %cond, <4 x i16> %val, <4 x i16> %neg
154  %res2 = add <4 x i16> %res, %t3
155  store <4 x i16> %res2, <4 x i16> addrspace(1)* %out, align 4
156  ret void
157}
158
159; GCN-LABEL: {{^}}s_min_max_v2i16:
160; GFX9: v_pk_max_i16
161; GFX9: v_pk_min_i16
162define amdgpu_kernel void @s_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) #0 {
163  %cond0 = icmp sgt <2 x i16> %val0, %val1
164  %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
165  %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
166
167  store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
168  store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
169  ret void
170}
171
172; GCN-LABEL: {{^}}v_min_max_v2i16:
173; GFX9: v_pk_max_i16
174; GFX9: v_pk_min_i16
175define amdgpu_kernel void @v_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
176  %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
177  %val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
178
179  %cond0 = icmp sgt <2 x i16> %val0, %val1
180  %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
181  %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
182
183  store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
184  store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
185  ret void
186}
187
188; GCN-LABEL: {{^}}s_min_max_v4i16:
189; GFX9: v_pk_max_i16
190; GFX9: v_pk_min_i16
191; GFX9: v_pk_max_i16
192; GFX9: v_pk_min_i16
193define amdgpu_kernel void @s_min_max_v4i16(<4 x i16> addrspace(1)* %out0, <4 x i16> addrspace(1)* %out1, <4 x i16> %val0, <4 x i16> %val1) #0 {
194  %cond0 = icmp sgt <4 x i16> %val0, %val1
195  %sel0 = select <4 x i1> %cond0, <4 x i16> %val0, <4 x i16> %val1
196  %sel1 = select <4 x i1> %cond0, <4 x i16> %val1, <4 x i16> %val0
197
198  store volatile <4 x i16> %sel0, <4 x i16> addrspace(1)* %out0, align 4
199  store volatile <4 x i16> %sel1, <4 x i16> addrspace(1)* %out1, align 4
200  ret void
201}
202
203; GCN-LABEL: {{^}}v_min_max_v2i16_user:
204define amdgpu_kernel void @v_min_max_v2i16_user(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> addrspace(1)* %ptr0, <2 x i16> addrspace(1)* %ptr1) #0 {
205  %val0 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr0
206  %val1 = load volatile <2 x i16>, <2 x i16> addrspace(1)* %ptr1
207
208  %cond0 = icmp sgt <2 x i16> %val0, %val1
209  %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
210  %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
211
212  store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
213  store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
214  store volatile <2 x i1> %cond0, <2 x i1> addrspace(1)* undef
215  ret void
216}
217
218; GCN-LABEL: {{^}}u_min_max_v2i16:
219; GFX9: v_pk_max_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
220; GFX9: v_pk_min_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
221define amdgpu_kernel void @u_min_max_v2i16(<2 x i16> addrspace(1)* %out0, <2 x i16> addrspace(1)* %out1, <2 x i16> %val0, <2 x i16> %val1) nounwind {
222  %cond0 = icmp ugt <2 x i16> %val0, %val1
223  %sel0 = select <2 x i1> %cond0, <2 x i16> %val0, <2 x i16> %val1
224  %sel1 = select <2 x i1> %cond0, <2 x i16> %val1, <2 x i16> %val0
225
226  store volatile <2 x i16> %sel0, <2 x i16> addrspace(1)* %out0, align 4
227  store volatile <2 x i16> %sel1, <2 x i16> addrspace(1)* %out1, align 4
228  ret void
229}
230
231declare i32 @llvm.amdgcn.workitem.id.x() #1
232
233attributes #0 = { nounwind }
234attributes #1 = { nounwind readnone }
235