1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
3; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
4; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
5; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
6
7; DEFAULT-LABEL: {{^}}main:
8; DEFAULT: s_load_dwordx4
9; DEFAULT: s_load_dwordx4
10; DEFAULT: s_waitcnt vmcnt(0)
11; DEFAULT: exp
12; DEFAULT: s_waitcnt lgkmcnt(0)
13; DEFAULT: s_endpgm
14define amdgpu_vs void @main(<16 x i8> addrspace(4)* inreg %arg, <16 x i8> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, <16 x i8> addrspace(4)* inreg %arg3, <16 x i8> addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(4)* inreg %constptr) #0 {
15main_body:
16  %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 0
17  %tmp10 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, !tbaa !0
18  %tmp10.cast = bitcast <16 x i8> %tmp10 to <4 x i32>
19  %tmp11 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp10.cast, i32 %arg6, i32 0, i1 false, i1 false)
20  %tmp12 = extractelement <4 x float> %tmp11, i32 0
21  %tmp13 = extractelement <4 x float> %tmp11, i32 1
22  call void @llvm.amdgcn.s.barrier() #1
23  %tmp14 = extractelement <4 x float> %tmp11, i32 2
24  %tmp15 = load float, float addrspace(4)* %constptr, align 4
25  %tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 1
26  %tmp17 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp16, !tbaa !0
27  %tmp17.cast = bitcast <16 x i8> %tmp17 to <4 x i32>
28  %tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp17.cast, i32 %arg6, i32 0, i1 false, i1 false)
29  %tmp19 = extractelement <4 x float> %tmp18, i32 0
30  %tmp20 = extractelement <4 x float> %tmp18, i32 1
31  %tmp21 = extractelement <4 x float> %tmp18, i32 2
32  %tmp22 = extractelement <4 x float> %tmp18, i32 3
33  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp19, float %tmp20, float %tmp21, float %tmp22, i1 false, i1 false) #0
34  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp12, float %tmp13, float %tmp14, float %tmp15, i1 true, i1 false) #0
35  ret void
36}
37
38; ILPMAX-LABEL: {{^}}main2:
39; ILPMAX: s_load_dwordx4
40; ILPMAX: s_waitcnt lgkmcnt(0)
41; ILPMAX: buffer_load
42; ILPMAX: s_load_dwordx4
43; ILPMAX: s_waitcnt lgkmcnt(0)
44; ILPMAX: buffer_load
45; ILPMAX: s_waitcnt vmcnt(0)
46; ILPMAX: exp pos0
47; ILPMAX-NEXT: exp param0
48; ILPMAX: s_endpgm
49define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(4)* byval %arg, [17 x <16 x i8>] addrspace(4)* byval %arg1, [17 x <4 x i32>] addrspace(4)* byval %arg2, [34 x <8 x i32>] addrspace(4)* byval %arg3, [16 x <16 x i8>] addrspace(4)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
50main_body:
51  %tmp = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 0
52  %tmp11 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, align 16, !tbaa !0
53  %tmp12 = add i32 %arg5, %arg7
54  %tmp11.cast = bitcast <16 x i8> %tmp11 to <4 x i32>
55  %tmp13 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp11.cast, i32 %tmp12, i32 0, i1 false, i1 false)
56  %tmp14 = extractelement <4 x float> %tmp13, i32 0
57  %tmp15 = extractelement <4 x float> %tmp13, i32 1
58  %tmp16 = extractelement <4 x float> %tmp13, i32 2
59  %tmp17 = extractelement <4 x float> %tmp13, i32 3
60  %tmp18 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 1
61  %tmp19 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp18, align 16, !tbaa !0
62  %tmp20 = add i32 %arg5, %arg7
63  %tmp19.cast = bitcast <16 x i8> %tmp19 to <4 x i32>
64  %tmp21 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp19.cast, i32 %tmp20, i32 0, i1 false, i1 false)
65  %tmp22 = extractelement <4 x float> %tmp21, i32 0
66  %tmp23 = extractelement <4 x float> %tmp21, i32 1
67  %tmp24 = extractelement <4 x float> %tmp21, i32 2
68  %tmp25 = extractelement <4 x float> %tmp21, i32 3
69  call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp14, float %tmp15, float %tmp16, float %tmp17, i1 false, i1 false) #0
70  call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp22, float %tmp23, float %tmp24, float %tmp25, i1 true, i1 false) #0
71  ret void
72}
73
74declare void @llvm.amdgcn.s.barrier() #1
75declare <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32>, i32, i32, i1, i1) #2
76declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
77
78attributes #0 = { nounwind }
79attributes #1 = { convergent nounwind }
80attributes #2 = { nounwind readonly }
81
82!0 = !{!1, !1, i64 0, i32 1}
83!1 = !{!"const", !2}
84!2 = !{!"tbaa root"}
85