1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE
3; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE
4
5define void @i24_or(i24* %a) {
6; LE-LABEL: i24_or:
7; LE:       @ %bb.0:
8; LE-NEXT:    ldrh r1, [r0]
9; LE-NEXT:    orr r1, r1, #384
10; LE-NEXT:    strh r1, [r0]
11; LE-NEXT:    mov pc, lr
12;
13; BE-LABEL: i24_or:
14; BE:       @ %bb.0:
15; BE-NEXT:    ldrh r1, [r0]
16; BE-NEXT:    ldrb r2, [r0, #2]
17; BE-NEXT:    orr r1, r2, r1, lsl #8
18; BE-NEXT:    orr r1, r1, #384
19; BE-NEXT:    strb r1, [r0, #2]
20; BE-NEXT:    lsr r1, r1, #8
21; BE-NEXT:    strh r1, [r0]
22; BE-NEXT:    mov pc, lr
23  %aa = load i24, i24* %a, align 1
24  %b = or i24 %aa, 384
25  store i24 %b, i24* %a, align 1
26  ret void
27}
28
29define void @i24_and_or(i24* %a) {
30; LE-LABEL: i24_and_or:
31; LE:       @ %bb.0:
32; LE-NEXT:    ldrh r1, [r0]
33; LE-NEXT:    mov r2, #16256
34; LE-NEXT:    orr r2, r2, #49152
35; LE-NEXT:    orr r1, r1, #384
36; LE-NEXT:    and r1, r1, r2
37; LE-NEXT:    strh r1, [r0]
38; LE-NEXT:    mov pc, lr
39;
40; BE-LABEL: i24_and_or:
41; BE:       @ %bb.0:
42; BE-NEXT:    mov r1, #128
43; BE-NEXT:    strb r1, [r0, #2]
44; BE-NEXT:    ldrh r1, [r0]
45; BE-NEXT:    orr r1, r1, #1
46; BE-NEXT:    strh r1, [r0]
47; BE-NEXT:    mov pc, lr
48  %b = load i24, i24* %a, align 1
49  %c = and i24 %b, -128
50  %d = or i24 %c, 384
51  store i24 %d, i24* %a, align 1
52  ret void
53}
54
55define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
56; LE-LABEL: i24_insert_bit:
57; LE:       @ %bb.0:
58; LE-NEXT:    mov r3, #255
59; LE-NEXT:    ldrh r2, [r0]
60; LE-NEXT:    orr r3, r3, #57088
61; LE-NEXT:    and r2, r2, r3
62; LE-NEXT:    orr r1, r2, r1, lsl #13
63; LE-NEXT:    strh r1, [r0]
64; LE-NEXT:    mov pc, lr
65;
66; BE-LABEL: i24_insert_bit:
67; BE:       @ %bb.0:
68; BE-NEXT:    ldrh r2, [r0]
69; BE-NEXT:    mov r3, #57088
70; BE-NEXT:    orr r3, r3, #16711680
71; BE-NEXT:    and r2, r3, r2, lsl #8
72; BE-NEXT:    orr r1, r2, r1, lsl #13
73; BE-NEXT:    lsr r1, r1, #8
74; BE-NEXT:    strh r1, [r0]
75; BE-NEXT:    mov pc, lr
76  %extbit = zext i1 %bit to i24
77  %b = load i24, i24* %a, align 1
78  %extbit.shl = shl nuw nsw i24 %extbit, 13
79  %c = and i24 %b, -8193
80  %d = or i24 %c, %extbit.shl
81  store i24 %d, i24* %a, align 1
82  ret void
83}
84
85define void @i56_or(i56* %a) {
86; LE-LABEL: i56_or:
87; LE:       @ %bb.0:
88; LE-NEXT:    ldr r1, [r0]
89; LE-NEXT:    orr r1, r1, #384
90; LE-NEXT:    str r1, [r0]
91; LE-NEXT:    mov pc, lr
92;
93; BE-LABEL: i56_or:
94; BE:       @ %bb.0:
95; BE-NEXT:    mov r1, r0
96; BE-NEXT:    ldr r12, [r0]
97; BE-NEXT:    ldrh r2, [r1, #4]!
98; BE-NEXT:    ldrb r3, [r1, #2]
99; BE-NEXT:    orr r2, r3, r2, lsl #8
100; BE-NEXT:    orr r2, r2, r12, lsl #24
101; BE-NEXT:    orr r2, r2, #384
102; BE-NEXT:    strb r2, [r1, #2]
103; BE-NEXT:    lsr r3, r2, #8
104; BE-NEXT:    strh r3, [r1]
105; BE-NEXT:    bic r1, r12, #255
106; BE-NEXT:    orr r1, r1, r2, lsr #24
107; BE-NEXT:    str r1, [r0]
108; BE-NEXT:    mov pc, lr
109  %aa = load i56, i56* %a
110  %b = or i56 %aa, 384
111  store i56 %b, i56* %a
112  ret void
113}
114
115define void @i56_and_or(i56* %a) {
116; LE-LABEL: i56_and_or:
117; LE:       @ %bb.0:
118; LE-NEXT:    ldr r1, [r0]
119; LE-NEXT:    orr r1, r1, #384
120; LE-NEXT:    bic r1, r1, #127
121; LE-NEXT:    str r1, [r0]
122; LE-NEXT:    mov pc, lr
123;
124; BE-LABEL: i56_and_or:
125; BE:       @ %bb.0:
126; BE-NEXT:    mov r1, r0
127; BE-NEXT:    ldr r12, [r0]
128; BE-NEXT:    ldrh r2, [r1, #4]!
129; BE-NEXT:    mov r3, #128
130; BE-NEXT:    strb r3, [r1, #2]
131; BE-NEXT:    lsl r2, r2, #8
132; BE-NEXT:    orr r2, r2, r12, lsl #24
133; BE-NEXT:    orr r2, r2, #384
134; BE-NEXT:    lsr r3, r2, #8
135; BE-NEXT:    strh r3, [r1]
136; BE-NEXT:    bic r1, r12, #255
137; BE-NEXT:    orr r1, r1, r2, lsr #24
138; BE-NEXT:    str r1, [r0]
139; BE-NEXT:    mov pc, lr
140
141  %b = load i56, i56* %a, align 1
142  %c = and i56 %b, -128
143  %d = or i56 %c, 384
144  store i56 %d, i56* %a, align 1
145  ret void
146}
147
148define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
149; LE-LABEL: i56_insert_bit:
150; LE:       @ %bb.0:
151; LE-NEXT:    ldr r2, [r0]
152; LE-NEXT:    bic r2, r2, #8192
153; LE-NEXT:    orr r1, r2, r1, lsl #13
154; LE-NEXT:    str r1, [r0]
155; LE-NEXT:    mov pc, lr
156;
157; BE-LABEL: i56_insert_bit:
158; BE:       @ %bb.0:
159; BE-NEXT:    .save {r11, lr}
160; BE-NEXT:    push {r11, lr}
161; BE-NEXT:    mov r2, r0
162; BE-NEXT:    ldr lr, [r0]
163; BE-NEXT:    ldrh r12, [r2, #4]!
164; BE-NEXT:    ldrb r3, [r2, #2]
165; BE-NEXT:    orr r12, r3, r12, lsl #8
166; BE-NEXT:    orr r3, r12, lr, lsl #24
167; BE-NEXT:    bic r3, r3, #8192
168; BE-NEXT:    orr r1, r3, r1, lsl #13
169; BE-NEXT:    lsr r3, r1, #8
170; BE-NEXT:    strh r3, [r2]
171; BE-NEXT:    bic r2, lr, #255
172; BE-NEXT:    orr r1, r2, r1, lsr #24
173; BE-NEXT:    str r1, [r0]
174; BE-NEXT:    pop {r11, lr}
175; BE-NEXT:    mov pc, lr
176  %extbit = zext i1 %bit to i56
177  %b = load i56, i56* %a, align 1
178  %extbit.shl = shl nuw nsw i56 %extbit, 13
179  %c = and i56 %b, -8193
180  %d = or i56 %c, %extbit.shl
181  store i56 %d, i56* %a, align 1
182  ret void
183}
184
185