1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
3
4define <4 x i32> @test1(<4 x i32> %a) nounwind {
5; CHECK-LABEL: test1:
6; CHECK:       @ %bb.0:
7; CHECK-NEXT:    vmov d17, r2, r3
8; CHECK-NEXT:    vmov d16, r0, r1
9; CHECK-NEXT:    vabs.s32 q8, q8
10; CHECK-NEXT:    vmov r0, r1, d16
11; CHECK-NEXT:    vmov r2, r3, d17
12; CHECK-NEXT:    mov pc, lr
13        %tmp1neg = sub <4 x i32> zeroinitializer, %a
14        %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
15        %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
16        ret <4 x i32> %abs
17}
18
19define <4 x i32> @test2(<4 x i32> %a) nounwind {
20; CHECK-LABEL: test2:
21; CHECK:       @ %bb.0:
22; CHECK-NEXT:    vmov d17, r2, r3
23; CHECK-NEXT:    vmov d16, r0, r1
24; CHECK-NEXT:    vabs.s32 q8, q8
25; CHECK-NEXT:    vmov r0, r1, d16
26; CHECK-NEXT:    vmov r2, r3, d17
27; CHECK-NEXT:    mov pc, lr
28        %tmp1neg = sub <4 x i32> zeroinitializer, %a
29        %b = icmp sge <4 x i32> %a, zeroinitializer
30        %abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
31        ret <4 x i32> %abs
32}
33
34define <8 x i16> @test3(<8 x i16> %a) nounwind {
35; CHECK-LABEL: test3:
36; CHECK:       @ %bb.0:
37; CHECK-NEXT:    vmov d17, r2, r3
38; CHECK-NEXT:    vmov d16, r0, r1
39; CHECK-NEXT:    vabs.s16 q8, q8
40; CHECK-NEXT:    vmov r0, r1, d16
41; CHECK-NEXT:    vmov r2, r3, d17
42; CHECK-NEXT:    mov pc, lr
43        %tmp1neg = sub <8 x i16> zeroinitializer, %a
44        %b = icmp sgt <8 x i16> %a, zeroinitializer
45        %abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
46        ret <8 x i16> %abs
47}
48
49define <16 x i8> @test4(<16 x i8> %a) nounwind {
50; CHECK-LABEL: test4:
51; CHECK:       @ %bb.0:
52; CHECK-NEXT:    vmov d17, r2, r3
53; CHECK-NEXT:    vmov d16, r0, r1
54; CHECK-NEXT:    vabs.s8 q8, q8
55; CHECK-NEXT:    vmov r0, r1, d16
56; CHECK-NEXT:    vmov r2, r3, d17
57; CHECK-NEXT:    mov pc, lr
58        %tmp1neg = sub <16 x i8> zeroinitializer, %a
59        %b = icmp slt <16 x i8> %a, zeroinitializer
60        %abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
61        ret <16 x i8> %abs
62}
63
64define <4 x i32> @test5(<4 x i32> %a) nounwind {
65; CHECK-LABEL: test5:
66; CHECK:       @ %bb.0:
67; CHECK-NEXT:    vmov d17, r2, r3
68; CHECK-NEXT:    vmov d16, r0, r1
69; CHECK-NEXT:    vabs.s32 q8, q8
70; CHECK-NEXT:    vmov r0, r1, d16
71; CHECK-NEXT:    vmov r2, r3, d17
72; CHECK-NEXT:    mov pc, lr
73        %tmp1neg = sub <4 x i32> zeroinitializer, %a
74        %b = icmp sle <4 x i32> %a, zeroinitializer
75        %abs = select <4 x i1> %b, <4 x i32> %tmp1neg, <4 x i32> %a
76        ret <4 x i32> %abs
77}
78
79define <2 x i32> @test6(<2 x i32> %a) nounwind {
80; CHECK-LABEL: test6:
81; CHECK:       @ %bb.0:
82; CHECK-NEXT:    vmov d16, r0, r1
83; CHECK-NEXT:    vabs.s32 d16, d16
84; CHECK-NEXT:    vmov r0, r1, d16
85; CHECK-NEXT:    mov pc, lr
86        %tmp1neg = sub <2 x i32> zeroinitializer, %a
87        %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
88        %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
89        ret <2 x i32> %abs
90}
91
92define <2 x i32> @test7(<2 x i32> %a) nounwind {
93; CHECK-LABEL: test7:
94; CHECK:       @ %bb.0:
95; CHECK-NEXT:    vmov d16, r0, r1
96; CHECK-NEXT:    vabs.s32 d16, d16
97; CHECK-NEXT:    vmov r0, r1, d16
98; CHECK-NEXT:    mov pc, lr
99        %tmp1neg = sub <2 x i32> zeroinitializer, %a
100        %b = icmp sge <2 x i32> %a, zeroinitializer
101        %abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
102        ret <2 x i32> %abs
103}
104
105define <4 x i16> @test8(<4 x i16> %a) nounwind {
106; CHECK-LABEL: test8:
107; CHECK:       @ %bb.0:
108; CHECK-NEXT:    vmov d16, r0, r1
109; CHECK-NEXT:    vabs.s16 d16, d16
110; CHECK-NEXT:    vmov r0, r1, d16
111; CHECK-NEXT:    mov pc, lr
112        %tmp1neg = sub <4 x i16> zeroinitializer, %a
113        %b = icmp sgt <4 x i16> %a, zeroinitializer
114        %abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
115        ret <4 x i16> %abs
116}
117
118define <8 x i8> @test9(<8 x i8> %a) nounwind {
119; CHECK-LABEL: test9:
120; CHECK:       @ %bb.0:
121; CHECK-NEXT:    vmov d16, r0, r1
122; CHECK-NEXT:    vabs.s8 d16, d16
123; CHECK-NEXT:    vmov r0, r1, d16
124; CHECK-NEXT:    mov pc, lr
125        %tmp1neg = sub <8 x i8> zeroinitializer, %a
126        %b = icmp slt <8 x i8> %a, zeroinitializer
127        %abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
128        ret <8 x i8> %abs
129}
130
131define <2 x i32> @test10(<2 x i32> %a) nounwind {
132; CHECK-LABEL: test10:
133; CHECK:       @ %bb.0:
134; CHECK-NEXT:    vmov d16, r0, r1
135; CHECK-NEXT:    vabs.s32 d16, d16
136; CHECK-NEXT:    vmov r0, r1, d16
137; CHECK-NEXT:    mov pc, lr
138        %tmp1neg = sub <2 x i32> zeroinitializer, %a
139        %b = icmp sle <2 x i32> %a, zeroinitializer
140        %abs = select <2 x i1> %b, <2 x i32> %tmp1neg, <2 x i32> %a
141        ret <2 x i32> %abs
142}
143
144;; Check that absdiff patterns as emitted by log2 shuffles are
145;; matched by VABD.
146
147define <4 x i32> @test11(<4 x i16> %a, <4 x i16> %b) nounwind {
148; CHECK-LABEL: test11:
149; CHECK:       @ %bb.0:
150; CHECK-NEXT:    vmov d16, r2, r3
151; CHECK-NEXT:    vmov d17, r0, r1
152; CHECK-NEXT:    vabdl.u16 q8, d17, d16
153; CHECK-NEXT:    vmov r0, r1, d16
154; CHECK-NEXT:    vmov r2, r3, d17
155; CHECK-NEXT:    mov pc, lr
156        %zext1 = zext <4 x i16> %a to <4 x i32>
157        %zext2 = zext <4 x i16> %b to <4 x i32>
158        %diff = sub <4 x i32> %zext1, %zext2
159        %shift1 = ashr <4 x i32> %diff, <i32 31, i32 31, i32 31, i32 31>
160        %add1 = add <4 x i32> %shift1, %diff
161        %res = xor <4 x i32> %shift1, %add1
162        ret <4 x i32> %res
163}
164define <8 x i16> @test12(<8 x i8> %a, <8 x i8> %b) nounwind {
165; CHECK-LABEL: test12:
166; CHECK:       @ %bb.0:
167; CHECK-NEXT:    vmov d16, r2, r3
168; CHECK-NEXT:    vmov d17, r0, r1
169; CHECK-NEXT:    vabdl.u8 q8, d17, d16
170; CHECK-NEXT:    vmov r0, r1, d16
171; CHECK-NEXT:    vmov r2, r3, d17
172; CHECK-NEXT:    mov pc, lr
173        %zext1 = zext <8 x i8> %a to <8 x i16>
174        %zext2 = zext <8 x i8> %b to <8 x i16>
175        %diff = sub <8 x i16> %zext1, %zext2
176        %shift1 = ashr <8 x i16> %diff,<i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
177        %add1 = add <8 x i16> %shift1, %diff
178        %res = xor <8 x i16> %shift1, %add1
179        ret <8 x i16> %res
180}
181
182define <2 x i64> @test13(<2 x i32> %a, <2 x i32> %b) nounwind {
183; CHECK-LABEL: test13:
184; CHECK:       @ %bb.0:
185; CHECK-NEXT:    vmov d16, r2, r3
186; CHECK-NEXT:    vmov d17, r0, r1
187; CHECK-NEXT:    vabdl.u32 q8, d17, d16
188; CHECK-NEXT:    vmov r0, r1, d16
189; CHECK-NEXT:    vmov r2, r3, d17
190; CHECK-NEXT:    mov pc, lr
191        %zext1 = zext <2 x i32> %a to <2 x i64>
192        %zext2 = zext <2 x i32> %b to <2 x i64>
193        %diff = sub <2 x i64> %zext1, %zext2
194        %shift1 = ashr <2 x i64> %diff,<i64 63, i64 63>
195        %add1 = add <2 x i64> %shift1, %diff
196        %res = xor <2 x i64> %shift1, %add1
197        ret <2 x i64> %res
198}
199