1# RUN: llc -o - %s -mtriple=armv7-- -verify-machineinstrs -run-pass=peephole-opt | FileCheck %s 2# 3# Make sure we do not crash on this input. 4# Note that this input could in principle be optimized, but right now we don't 5# have this case implemented so the output should simply be unchanged. 6# 7# CHECK-LABEL: name: func 8# CHECK: body: | 9# CHECK: bb.0: 10# CHECK: Bcc %bb.2, 1, undef $cpsr 11# 12# CHECK: bb.1: 13# CHECK: %0:dpr = IMPLICIT_DEF 14# CHECK: %1:gpr, %2:gpr = VMOVRRD %0, 14, $noreg 15# CHECK: B %bb.3 16# 17# CHECK: bb.2: 18# CHECK: %3:spr = IMPLICIT_DEF 19# CHECK: %4:gpr = VMOVRS %3, 14, $noreg 20# 21# CHECK: bb.3: 22# CHECK: %5:gpr = PHI %1, %bb.1, %4, %bb.2 23# CHECK: %6:spr = VMOVSR %5, 14, $noreg 24--- 25name: func0 26tracksRegLiveness: true 27body: | 28 bb.0: 29 Bcc %bb.2, 1, undef $cpsr 30 31 bb.1: 32 %0:dpr = IMPLICIT_DEF 33 %1:gpr, %2:gpr = VMOVRRD %0:dpr, 14, $noreg 34 B %bb.3 35 36 bb.2: 37 %3:spr = IMPLICIT_DEF 38 %4:gpr = VMOVRS %3:spr, 14, $noreg 39 40 bb.3: 41 %5:gpr = PHI %1, %bb.1, %4, %bb.2 42 %6:spr = VMOVSR %5, 14, $noreg 43... 44 45# CHECK-LABEL: name: func1 46# CHECK: %6:spr = PHI %0, %bb.1, %2, %bb.2 47# CHEKC: %7:spr = COPY %6 48--- 49name: func1 50tracksRegLiveness: true 51body: | 52 bb.0: 53 Bcc %bb.2, 1, undef $cpsr 54 55 bb.1: 56 %1:spr = IMPLICIT_DEF 57 %0:gpr = VMOVRS %1, 14, $noreg 58 B %bb.3 59 60 bb.2: 61 %3:spr = IMPLICIT_DEF 62 %2:gpr = VMOVRS %3:spr, 14, $noreg 63 64 bb.3: 65 %4:gpr = PHI %0, %bb.1, %2, %bb.2 66 %5:spr = VMOVSR %4, 14, $noreg 67... 68 69# The current implementation doesn't perform any transformations if undef 70# operands are involved. 71# CHECK-LABEL: name: func-undefops 72# CHECK: body: | 73# CHECK: bb.0: 74# CHECK: Bcc %bb.2, 1, undef $cpsr 75# 76# CHECK: bb.1: 77# CHECK: %0:gpr = VMOVRS undef %1:spr, 14, $noreg 78# CHECK: B %bb.3 79# 80# CHECK: bb.2: 81# CHECK: %2:gpr = VMOVRS undef %3:spr, 14, $noreg 82# 83# CHECK: bb.3: 84# CHECK: %4:gpr = PHI %0, %bb.1, %2, %bb.2 85# CHECK: %5:spr = VMOVSR %4, 14, $noreg 86--- 87name: func-undefops 88tracksRegLiveness: true 89body: | 90 bb.0: 91 Bcc %bb.2, 1, undef $cpsr 92 93 bb.1: 94 %0:gpr = VMOVRS undef %1:spr, 14, $noreg 95 B %bb.3 96 97 bb.2: 98 %2:gpr = VMOVRS undef %3:spr, 14, $noreg 99 100 bb.3: 101 %4:gpr = PHI %0, %bb.1, %2, %bb.2 102 %5:spr = VMOVSR %4, 14, $noreg 103... 104