1; RUN: opt -mtriple=arm-arm-eabi -mcpu=cortex-m33 < %s -arm-parallel-dsp -S | FileCheck %s
2;
3; Operands of both muls are not symmetrical (see also comments inlined below), check
4; that the rewrite isn't triggered.
5;
6; CHECK-NOT:  call i32 @llvm.arm.smlad
7;
8define dso_local i32 @test(i32 %arg, i32* nocapture readnone %arg1, i16* nocapture readonly %arg2, i16* nocapture readonly %arg3) {
9entry:
10  %cmp24 = icmp sgt i32 %arg, 0
11  br i1 %cmp24, label %for.body.preheader, label %for.cond.cleanup
12
13for.body.preheader:
14  %.pre = load i16, i16* %arg3, align 2
15  %.pre27 = load i16, i16* %arg2, align 2
16  br label %for.body
17
18for.cond.cleanup:
19  %mac1.0.lcssa = phi i32 [ 0, %entry ], [ %add11, %for.body ]
20  ret i32 %mac1.0.lcssa
21
22for.body:
23  %mac1.026 = phi i32 [ %add11, %for.body ], [ 0, %for.body.preheader ]
24  %i.025 = phi i32 [ %add, %for.body ], [ 0, %for.body.preheader ]
25  %arrayidx = getelementptr inbounds i16, i16* %arg3, i32 %i.025
26  %0 = load i16, i16* %arrayidx, align 2
27  %add = add nuw nsw i32 %i.025, 1
28  %arrayidx1 = getelementptr inbounds i16, i16* %arg3, i32 %add
29  %1 = load i16, i16* %arrayidx1, align 2
30  %arrayidx3 = getelementptr inbounds i16, i16* %arg2, i32 %i.025
31  %2 = load i16, i16* %arrayidx3, align 2
32  %conv = sext i16 %2 to i32
33
34; This zero-extends the 2nd operand of %mul:
35  %conv4 = zext i16 %0 to i32
36
37  %mul = mul nsw i32 %conv, %conv4
38  %arrayidx6 = getelementptr inbounds i16, i16* %arg2, i32 %add
39  %3 = load i16, i16* %arrayidx6, align 2
40
41; And here we only have sign-extensions. Thus, the operands of
42; %mul and %mul9 are not symmetrical:
43  %conv7 = sext i16 %3 to i32
44  %conv8 = sext i16 %1 to i32
45
46  %mul9 = mul nsw i32 %conv7, %conv8
47  %add10 = add i32 %mul, %mac1.026
48  %add11 = add i32 %add10, %mul9
49  %exitcond = icmp ne i32 %add, %arg
50  br i1 %exitcond, label %for.body, label %for.cond.cleanup
51}
52