1# RUN: llc -run-pass=arm-cp-islands -o - %s | FileCheck %s
2
3# Test created by tweaking the register allocation after stopping the IR below
4# just before constant islands. We were forwarding the table index to the end of
5# the block, even though the LEA clobbered it.
6
7# CHECK-LABEL: name: foo
8# CHECK:     tBR_JT
9  # This order is important. If the jump-table comes first then the
10  # transformation is valid because the LEA can be removed, see second test.
11# CHECK:     CONSTPOOL_ENTRY
12# CHECK:     JUMPTABLE_ADDRS
13
14# CHECK-LABEL: name: bar
15# CHECK: tTBB_JT $pc, killed $r1
16
17--- |
18  ; ModuleID = 'simple.ll'
19  source_filename = "simple.ll"
20  target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
21  target triple = "thumbv6m-none--eabi"
22
23  define void @foo(i8 %in, i32* %addr) {
24    store i32 12345678, i32* %addr
25    %1 = call i32 @llvm.arm.space(i32 980, i32 undef)
26    %2 = zext i8 %in to i32
27    switch i32 %2, label %default [
28      i32 0, label %d1
29      i32 1, label %d2
30      i32 3, label %d3
31      i32 4, label %d4
32      i32 5, label %d5
33      i32 6, label %d6
34      i32 7, label %d7
35      i32 2, label %d8
36      i32 8, label %d9
37      i32 9, label %d10
38      i32 19, label %d11
39      i32 20, label %d12
40      i32 21, label %d13
41      i32 22, label %d14
42      i32 24, label %d15
43      i32 25, label %d16
44      i32 26, label %d17
45    ]
46
47  default:                                          ; preds = %0
48    unreachable
49
50  d1:                                               ; preds = %0
51    unreachable
52
53  d2:                                               ; preds = %0
54    unreachable
55
56  d3:                                               ; preds = %0
57    unreachable
58
59  d4:                                               ; preds = %0
60    unreachable
61
62  d5:                                               ; preds = %0
63    unreachable
64
65  d6:                                               ; preds = %0
66    unreachable
67
68  d7:                                               ; preds = %0
69    unreachable
70
71  d8:                                               ; preds = %0
72    unreachable
73
74  d9:                                               ; preds = %0
75    unreachable
76
77  d10:                                              ; preds = %0
78    unreachable
79
80  d11:                                              ; preds = %0
81    unreachable
82
83  d12:                                              ; preds = %0
84    unreachable
85
86  d13:                                              ; preds = %0
87    unreachable
88
89  d14:                                              ; preds = %0
90    unreachable
91
92  d15:                                              ; preds = %0
93    unreachable
94
95  d16:                                              ; preds = %0
96    unreachable
97
98  d17:                                              ; preds = %0
99    unreachable
100  }
101
102  define void @bar(i8 %in, i32* %addr) {
103      store i32 12345678, i32* %addr
104    %1 = zext i8 %in to i32
105    switch i32 %1, label %default [
106      i32 0, label %d1
107      i32 1, label %d2
108      i32 3, label %d3
109      i32 4, label %d4
110      i32 5, label %d5
111      i32 6, label %d6
112      i32 7, label %d7
113      i32 2, label %d8
114      i32 8, label %d9
115      i32 9, label %d10
116      i32 19, label %d11
117      i32 20, label %d12
118      i32 21, label %d13
119      i32 22, label %d14
120      i32 24, label %d15
121      i32 25, label %d16
122      i32 26, label %d17
123    ]
124
125  default:                                          ; preds = %0
126    unreachable
127
128  d1:                                               ; preds = %0
129    unreachable
130
131  d2:                                               ; preds = %0
132    unreachable
133
134  d3:                                               ; preds = %0
135    unreachable
136
137  d4:                                               ; preds = %0
138    unreachable
139
140  d5:                                               ; preds = %0
141    unreachable
142
143  d6:                                               ; preds = %0
144    unreachable
145
146  d7:                                               ; preds = %0
147    unreachable
148
149  d8:                                               ; preds = %0
150    unreachable
151
152  d9:                                               ; preds = %0
153    unreachable
154
155  d10:                                              ; preds = %0
156    unreachable
157
158  d11:                                              ; preds = %0
159    unreachable
160
161  d12:                                              ; preds = %0
162    unreachable
163
164  d13:                                              ; preds = %0
165    unreachable
166
167  d14:                                              ; preds = %0
168    unreachable
169
170  d15:                                              ; preds = %0
171    unreachable
172
173  d16:                                              ; preds = %0
174    unreachable
175
176  d17:                                              ; preds = %0
177    unreachable
178  }
179
180  ; Function Attrs: nounwind
181  declare i32 @llvm.arm.space(i32, i32) #0
182
183  ; Function Attrs: nounwind
184  declare void @llvm.stackprotector(i8*, i8**) #0
185
186  attributes #0 = { nounwind }
187
188...
189---
190name:            foo
191alignment:       1
192exposesReturnsTwice: false
193legalized:       false
194regBankSelected: false
195selected:        false
196tracksRegLiveness: true
197liveins:
198  - { reg: '$r0' }
199  - { reg: '$r1' }
200frameInfo:
201  isFrameAddressTaken: false
202  isReturnAddressTaken: false
203  hasStackMap:     false
204  hasPatchPoint:   false
205  stackSize:       0
206  offsetAdjustment: 0
207  maxAlignment:    0
208  adjustsStack:    false
209  hasCalls:        false
210  maxCallFrameSize: 0
211  hasOpaqueSPAdjustment: false
212  hasVAStart:      false
213  hasMustTailInVarArgFunc: false
214constants:
215  - id:              0
216    value:           i32 12345678
217    alignment:       4
218jumpTable:
219  kind:            inline
220  entries:
221    - id:              0
222      blocks:          [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4',
223                         '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
224                         '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
225                         '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
226                         '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
227                         '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
228                         '%bb.17.d16', '%bb.18.d17' ]
229body:             |
230  bb.0 (%ir-block.0):
231    successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
232    liveins: $r0, $r1
233
234    $r2 = tLDRpci %const.0, 14, $noreg
235    tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
236    dead $r1 = SPACE 980, undef $r0
237    $r0 = tUXTB killed $r0, 14, $noreg
238    $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
239    tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
240    tBcc %bb.2.d1, 8, killed $cpsr
241
242  bb.1 (%ir-block.0):
243    successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
244    liveins: $r1
245
246    $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
247    $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
248    $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
249    tBR_JTr killed $r0, %jump-table.0
250
251  bb.3.d2:
252
253  bb.9.d8:
254
255  bb.4.d3:
256
257  bb.5.d4:
258
259  bb.6.d5:
260
261  bb.7.d6:
262
263  bb.8.d7:
264
265  bb.10.d9:
266
267  bb.11.d10:
268
269  bb.2.d1:
270
271  bb.12.d11:
272
273  bb.13.d12:
274
275  bb.14.d13:
276
277  bb.15.d14:
278
279  bb.16.d15:
280
281  bb.17.d16:
282
283  bb.18.d17:
284
285...
286
287---
288name:            bar
289alignment:       1
290exposesReturnsTwice: false
291legalized:       false
292regBankSelected: false
293selected:        false
294tracksRegLiveness: true
295liveins:
296  - { reg: '$r0' }
297  - { reg: '$r1' }
298frameInfo:
299  isFrameAddressTaken: false
300  isReturnAddressTaken: false
301  hasStackMap:     false
302  hasPatchPoint:   false
303  stackSize:       0
304  offsetAdjustment: 0
305  maxAlignment:    0
306  adjustsStack:    false
307  hasCalls:        false
308  maxCallFrameSize: 0
309  hasOpaqueSPAdjustment: false
310  hasVAStart:      false
311  hasMustTailInVarArgFunc: false
312constants:
313  - id:              0
314    value:           i32 12345678
315    alignment:       4
316jumpTable:
317  kind:            inline
318  entries:
319    - id:              0
320      blocks:          [ '%bb.3.d2', '%bb.9.d8', '%bb.4.d3', '%bb.5.d4',
321                         '%bb.6.d5', '%bb.7.d6', '%bb.8.d7', '%bb.10.d9',
322                         '%bb.11.d10', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
323                         '%bb.2.d1', '%bb.2.d1', '%bb.2.d1', '%bb.2.d1',
324                         '%bb.2.d1', '%bb.2.d1', '%bb.12.d11', '%bb.13.d12',
325                         '%bb.14.d13', '%bb.15.d14', '%bb.2.d1', '%bb.16.d15',
326                         '%bb.17.d16', '%bb.18.d17' ]
327body:             |
328  bb.0 (%ir-block.0):
329    successors: %bb.2.d1(0x03c3c3c4), %bb.1(0x7c3c3c3c)
330    liveins: $r0, $r1
331
332    $r2 = tLDRpci %const.0, 14, $noreg
333    tSTRi killed $r2, killed $r1, 0, 14, $noreg :: (store 4 into %ir.addr)
334    $r0 = tUXTB killed $r0, 14, $noreg
335    $r1, dead $cpsr = tSUBi3 killed $r0, 1, 14, $noreg
336    tCMPi8 $r1, 25, 14, $noreg, implicit-def $cpsr
337    tBcc %bb.2.d1, 8, killed $cpsr
338
339  bb.1 (%ir-block.0):
340    successors: %bb.3.d2(0x07c549d2), %bb.9.d8(0x07c549d2), %bb.4.d3(0x07c549d2), %bb.5.d4(0x07c549d2), %bb.6.d5(0x07c549d2), %bb.7.d6(0x07c549d2), %bb.8.d7(0x07c549d2), %bb.10.d9(0x07c549d2), %bb.11.d10(0x07c549d2), %bb.2.d1(0x03ab62db), %bb.12.d11(0x07c549d2), %bb.13.d12(0x07c549d2), %bb.14.d13(0x07c549d2), %bb.15.d14(0x07c549d2), %bb.16.d15(0x07c549d2), %bb.17.d16(0x07c549d2), %bb.18.d17(0x07c549d2)
341    liveins: $r1
342
343    $r0, dead $cpsr = tLSLri killed $r1, 2, 14, $noreg
344    $r1 = tLEApcrelJT %jump-table.0, 14, $noreg
345    $r0 = tLDRr killed $r1, killed $r0, 14, $noreg :: (load 4 from jump-table)
346    tBR_JTr killed $r0, %jump-table.0
347
348  bb.3.d2:
349
350  bb.9.d8:
351
352  bb.4.d3:
353
354  bb.5.d4:
355
356  bb.6.d5:
357
358  bb.7.d6:
359
360  bb.8.d7:
361
362  bb.10.d9:
363
364  bb.11.d10:
365
366  bb.2.d1:
367
368  bb.12.d11:
369
370  bb.13.d12:
371
372  bb.14.d13:
373
374  bb.15.d14:
375
376  bb.16.d15:
377
378  bb.17.d16:
379
380  bb.18.d17:
381
382...
383