1; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s 2 3%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } 4%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } 5%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } 6%struct.__neon_float32x2x4_t = type { <2 x float>, <2 x float>, <2 x float>, <2 x float> } 7%struct.__neon_int64x1x4_t = type { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } 8 9%struct.__neon_int8x16x4_t = type { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } 10%struct.__neon_int16x8x4_t = type { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } 11%struct.__neon_int32x4x4_t = type { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } 12%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> } 13 14define <8 x i8> @vld4i8(i8* %A) nounwind { 15;CHECK-LABEL: vld4i8: 16;Check the alignment value. Max for this instruction is 256 bits: 17;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:64] 18 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 8) 19 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 20 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 21 %tmp4 = add <8 x i8> %tmp2, %tmp3 22 ret <8 x i8> %tmp4 23} 24 25;Check for a post-increment updating load with register increment. 26define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { 27;CHECK-LABEL: vld4i8_update: 28;CHECK: vld4.8 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128], r1 29 %A = load i8*, i8** %ptr 30 %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8* %A, i32 16) 31 %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 32 %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 33 %tmp4 = add <8 x i8> %tmp2, %tmp3 34 %tmp5 = getelementptr i8, i8* %A, i32 %inc 35 store i8* %tmp5, i8** %ptr 36 ret <8 x i8> %tmp4 37} 38 39define <4 x i16> @vld4i16(i16* %A) nounwind { 40;CHECK-LABEL: vld4i16: 41;Check the alignment value. Max for this instruction is 256 bits: 42;CHECK: vld4.16 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:128] 43 %tmp0 = bitcast i16* %A to i8* 44 %tmp1 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8* %tmp0, i32 16) 45 %tmp2 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 0 46 %tmp3 = extractvalue %struct.__neon_int16x4x4_t %tmp1, 2 47 %tmp4 = add <4 x i16> %tmp2, %tmp3 48 ret <4 x i16> %tmp4 49} 50 51define <2 x i32> @vld4i32(i32* %A) nounwind { 52;CHECK-LABEL: vld4i32: 53;Check the alignment value. Max for this instruction is 256 bits: 54;CHECK: vld4.32 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256] 55 %tmp0 = bitcast i32* %A to i8* 56 %tmp1 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8* %tmp0, i32 32) 57 %tmp2 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 0 58 %tmp3 = extractvalue %struct.__neon_int32x2x4_t %tmp1, 2 59 %tmp4 = add <2 x i32> %tmp2, %tmp3 60 ret <2 x i32> %tmp4 61} 62 63define <2 x float> @vld4f(float* %A) nounwind { 64;CHECK-LABEL: vld4f: 65;CHECK: vld4.32 66 %tmp0 = bitcast float* %A to i8* 67 %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8* %tmp0, i32 1) 68 %tmp2 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 0 69 %tmp3 = extractvalue %struct.__neon_float32x2x4_t %tmp1, 2 70 %tmp4 = fadd <2 x float> %tmp2, %tmp3 71 ret <2 x float> %tmp4 72} 73 74define <1 x i64> @vld4i64(i64* %A) nounwind { 75;CHECK-LABEL: vld4i64: 76;Check the alignment value. Max for this instruction is 256 bits: 77;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256] 78 %tmp0 = bitcast i64* %A to i8* 79 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64) 80 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 81 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 82 %tmp4 = add <1 x i64> %tmp2, %tmp3 83 ret <1 x i64> %tmp4 84} 85 86define <1 x i64> @vld4i64_update(i64** %ptr, i64* %A) nounwind { 87;CHECK-LABEL: vld4i64_update: 88;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256]! 89 %tmp0 = bitcast i64* %A to i8* 90 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64) 91 %tmp5 = getelementptr i64, i64* %A, i32 4 92 store i64* %tmp5, i64** %ptr 93 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 94 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 95 %tmp4 = add <1 x i64> %tmp2, %tmp3 96 ret <1 x i64> %tmp4 97} 98 99define <1 x i64> @vld4i64_reg_update(i64** %ptr, i64* %A) nounwind { 100;CHECK-LABEL: vld4i64_reg_update: 101;CHECK: vld1.64 {d16, d17, d18, d19}, [{{r[0-9]+|lr}}:256], {{r[0-9]+|lr}} 102 %tmp0 = bitcast i64* %A to i8* 103 %tmp1 = call %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8* %tmp0, i32 64) 104 %tmp5 = getelementptr i64, i64* %A, i32 1 105 store i64* %tmp5, i64** %ptr 106 %tmp2 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 0 107 %tmp3 = extractvalue %struct.__neon_int64x1x4_t %tmp1, 2 108 %tmp4 = add <1 x i64> %tmp2, %tmp3 109 ret <1 x i64> %tmp4 110} 111 112define <16 x i8> @vld4Qi8(i8* %A) nounwind { 113;CHECK-LABEL: vld4Qi8: 114;Check the alignment value. Max for this instruction is 256 bits: 115;CHECK: vld4.8 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:256]! 116;CHECK: vld4.8 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:256] 117 %tmp1 = call %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8* %A, i32 64) 118 %tmp2 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 0 119 %tmp3 = extractvalue %struct.__neon_int8x16x4_t %tmp1, 2 120 %tmp4 = add <16 x i8> %tmp2, %tmp3 121 ret <16 x i8> %tmp4 122} 123 124define <8 x i16> @vld4Qi16(i16* %A) nounwind { 125;CHECK-LABEL: vld4Qi16: 126;Check for no alignment specifier. 127;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}]! 128;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}] 129 %tmp0 = bitcast i16* %A to i8* 130 %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 1) 131 %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 132 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 133 %tmp4 = add <8 x i16> %tmp2, %tmp3 134 ret <8 x i16> %tmp4 135} 136 137;Check for a post-increment updating load. 138define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { 139;CHECK-LABEL: vld4Qi16_update: 140;CHECK: vld4.16 {d16, d18, d20, d22}, [{{r[0-9]+|lr}}:64]! 141;CHECK: vld4.16 {d17, d19, d21, d23}, [{{r[0-9]+|lr}}:64]! 142 %A = load i16*, i16** %ptr 143 %tmp0 = bitcast i16* %A to i8* 144 %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8* %tmp0, i32 8) 145 %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 146 %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 147 %tmp4 = add <8 x i16> %tmp2, %tmp3 148 %tmp5 = getelementptr i16, i16* %A, i32 32 149 store i16* %tmp5, i16** %ptr 150 ret <8 x i16> %tmp4 151} 152 153define <4 x i32> @vld4Qi32(i32* %A) nounwind { 154;CHECK-LABEL: vld4Qi32: 155;CHECK: vld4.32 156;CHECK: vld4.32 157 %tmp0 = bitcast i32* %A to i8* 158 %tmp1 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8* %tmp0, i32 1) 159 %tmp2 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 0 160 %tmp3 = extractvalue %struct.__neon_int32x4x4_t %tmp1, 2 161 %tmp4 = add <4 x i32> %tmp2, %tmp3 162 ret <4 x i32> %tmp4 163} 164 165define <4 x float> @vld4Qf(float* %A) nounwind { 166;CHECK-LABEL: vld4Qf: 167;CHECK: vld4.32 168;CHECK: vld4.32 169 %tmp0 = bitcast float* %A to i8* 170 %tmp1 = call %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8* %tmp0, i32 1) 171 %tmp2 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 0 172 %tmp3 = extractvalue %struct.__neon_float32x4x4_t %tmp1, 2 173 %tmp4 = fadd <4 x float> %tmp2, %tmp3 174 ret <4 x float> %tmp4 175} 176 177declare %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8.p0i8(i8*, i32) nounwind readonly 178declare %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4.v4i16.p0i8(i8*, i32) nounwind readonly 179declare %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4.v2i32.p0i8(i8*, i32) nounwind readonly 180declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32.p0i8(i8*, i32) nounwind readonly 181declare %struct.__neon_int64x1x4_t @llvm.arm.neon.vld4.v1i64.p0i8(i8*, i32) nounwind readonly 182 183declare %struct.__neon_int8x16x4_t @llvm.arm.neon.vld4.v16i8.p0i8(i8*, i32) nounwind readonly 184declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16.p0i8(i8*, i32) nounwind readonly 185declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4.v4i32.p0i8(i8*, i32) nounwind readonly 186declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4.v4f32.p0i8(i8*, i32) nounwind readonly 187