1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; CHECK-LABEL: t00
4; CHECK: and(q{{[0-3]}},q{{[0-3]}})
5define <128 x i8> @t00(<128 x i8> %a0, <128 x i8> %a1) #0 {
6  %q0 = trunc <128 x i8> %a0 to <128 x i1>
7  %q1 = trunc <128 x i8> %a1 to <128 x i1>
8  %q2 = and <128 x i1> %q0, %q1
9  %v0 = zext <128 x i1> %q2 to <128 x i8>
10  ret <128 x i8> %v0
11}
12
13declare <1024 x i1> @llvm.hexagon.vandvrt.128B(<128 x i8>, i32)
14
15; CHECK-LABEL: t01
16; CHECK: or(q{{[0-3]}},q{{[0-3]}})
17define <128 x i8> @t01(<128 x i8> %a0, <128 x i8> %a1) #0 {
18  %q0 = trunc <128 x i8> %a0 to <128 x i1>
19  %q1 = trunc <128 x i8> %a1 to <128 x i1>
20  %q2 = or <128 x i1> %q0, %q1
21  %v0 = zext <128 x i1> %q2 to <128 x i8>
22  ret <128 x i8> %v0
23}
24
25; CHECK-LABEL: t02
26; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
27define <128 x i8> @t02(<128 x i8> %a0, <128 x i8> %a1) #0 {
28  %q0 = trunc <128 x i8> %a0 to <128 x i1>
29  %q1 = trunc <128 x i8> %a1 to <128 x i1>
30  %q2 = xor <128 x i1> %q0, %q1
31  %v0 = zext <128 x i1> %q2 to <128 x i8>
32  ret <128 x i8> %v0
33}
34
35; CHECK-LABEL: t10
36; CHECK: and(q{{[0-3]}},q{{[0-3]}})
37define <64 x i16> @t10(<64 x i16> %a0, <64 x i16> %a1) #0 {
38  %q0 = trunc <64 x i16> %a0 to <64 x i1>
39  %q1 = trunc <64 x i16> %a1 to <64 x i1>
40  %q2 = and <64 x i1> %q0, %q1
41  %v0 = zext <64 x i1> %q2 to <64 x i16>
42  ret <64 x i16> %v0
43}
44
45; CHECK-LABEL: t11
46; CHECK: or(q{{[0-3]}},q{{[0-3]}})
47define <64 x i16> @t11(<64 x i16> %a0, <64 x i16> %a1) #0 {
48  %q0 = trunc <64 x i16> %a0 to <64 x i1>
49  %q1 = trunc <64 x i16> %a1 to <64 x i1>
50  %q2 = or <64 x i1> %q0, %q1
51  %v0 = zext <64 x i1> %q2 to <64 x i16>
52  ret <64 x i16> %v0
53}
54
55; CHECK-LABEL: t12
56; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
57define <64 x i16> @t12(<64 x i16> %a0, <64 x i16> %a1) #0 {
58  %q0 = trunc <64 x i16> %a0 to <64 x i1>
59  %q1 = trunc <64 x i16> %a1 to <64 x i1>
60  %q2 = xor <64 x i1> %q0, %q1
61  %v0 = zext <64 x i1> %q2 to <64 x i16>
62  ret <64 x i16> %v0
63}
64
65; CHECK-LABEL: t20
66; CHECK: and(q{{[0-3]}},q{{[0-3]}})
67define <32 x i32> @t20(<32 x i32> %a0, <32 x i32> %a1) #0 {
68  %q0 = trunc <32 x i32> %a0 to <32 x i1>
69  %q1 = trunc <32 x i32> %a1 to <32 x i1>
70  %q2 = and <32 x i1> %q0, %q1
71  %v0 = zext <32 x i1> %q2 to <32 x i32>
72  ret <32 x i32> %v0
73}
74
75; CHECK-LABEL: t21
76; CHECK: or(q{{[0-3]}},q{{[0-3]}})
77define <32 x i32> @t21(<32 x i32> %a0, <32 x i32> %a1) #0 {
78  %q0 = trunc <32 x i32> %a0 to <32 x i1>
79  %q1 = trunc <32 x i32> %a1 to <32 x i1>
80  %q2 = or <32 x i1> %q0, %q1
81  %v0 = zext <32 x i1> %q2 to <32 x i32>
82  ret <32 x i32> %v0
83}
84
85; CHECK-LABEL: t22
86; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
87define <32 x i32> @t22(<32 x i32> %a0, <32 x i32> %a1) #0 {
88  %q0 = trunc <32 x i32> %a0 to <32 x i1>
89  %q1 = trunc <32 x i32> %a1 to <32 x i1>
90  %q2 = xor <32 x i1> %q0, %q1
91  %v0 = zext <32 x i1> %q2 to <32 x i32>
92  ret <32 x i32> %v0
93}
94
95attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
96