1; RUN: llc -march=hexagon < %s
2; REQUIRES: asserts
3
4; Test that the compiler doesn't assert because the live interval information
5; isn't updated correctly during the Hexagon Expand Condsets pass. The pass
6; wasn't updating the information when converting a mux with the same operands
7; into a copy. When this occurs, the pass needs to update the liveness
8; information for the predicate register, which is removed.
9
10define void @f0(i32 %a0) unnamed_addr {
11b0:
12  %v0 = or i32 undef, %a0
13  %v1 = or i32 undef, %v0
14  br label %b1
15
16b1:                                               ; preds = %b3, %b0
17  %v2 = phi i32 [ %v9, %b3 ], [ 0, %b0 ]
18  %v3 = phi i32 [ 0, %b3 ], [ %v1, %b0 ]
19  %v4 = srem i32 %v2, 4
20  %v5 = icmp eq i32 %v4, 0
21  %v6 = select i1 %v5, i32 %v1, i32 %v3
22  %v7 = shl i32 %v6, 8
23  %v8 = add i32 0, %v7
24  br i1 undef, label %b2, label %b3
25
26b2:                                               ; preds = %b1
27  store i32 %v8, i32* undef, align 4
28  br label %b3
29
30b3:                                               ; preds = %b2, %b1
31  %v9 = add nuw nsw i32 %v2, 1
32  %v10 = icmp slt i32 %v9, undef
33  br i1 %v10, label %b1, label %b4
34
35b4:                                               ; preds = %b3
36  unreachable
37}
38