1; RUN: llc -march=hexagon -O2 < %s
2; REQUIRES: asserts
3
4; Test that the dead and kill flags are not added incorrectly during the
5; Hexagon Expand Condsets pass. The pass shouldn't add a kill flag to a use that
6; is tied to a definition, and the pass shouldn't remove the dead flag for a
7; definition that is really dead. The removal of the dead flag causes an assert
8; in the Machine Scheduler when querying live interval information.
9
10define void @f0() #0 {
11b0:
12  br label %b1
13
14b1:                                               ; preds = %b3, %b0
15  %v0 = load i16, i16* undef, align 4
16  %v1 = sext i16 %v0 to i32
17  %v2 = and i32 %v1, 7
18  %v3 = sub nsw i32 8, %v2
19  %v4 = sub nsw i32 8, 0
20  br label %b2
21
22b2:                                               ; preds = %b2, %b1
23  %v5 = phi i8* [ undef, %b1 ], [ %v16, %b2 ]
24  %v6 = phi i32 [ 4, %b1 ], [ %v17, %b2 ]
25  %v7 = load i8, i8* undef, align 1
26  %v8 = zext i8 %v7 to i32
27  %v9 = mul nuw nsw i32 %v8, %v3
28  %v10 = add nuw nsw i32 0, %v9
29  %v11 = mul nuw nsw i32 %v10, %v4
30  %v12 = add nuw nsw i32 0, %v11
31  %v13 = lshr i32 %v12, 6
32  %v14 = trunc i32 %v13 to i8
33  store i8 %v14, i8* %v5, align 1
34  %v15 = getelementptr inbounds i8, i8* %v5, i32 1
35  %v16 = select i1 undef, i8* undef, i8* %v15
36  %v17 = add nsw i32 %v6, -1
37  %v18 = icmp eq i32 %v17, 0
38  br i1 %v18, label %b3, label %b2
39
40b3:                                               ; preds = %b2
41  br i1 undef, label %b1, label %b4
42
43b4:                                               ; preds = %b3
44  ret void
45}
46
47attributes #0 = { nounwind "target-cpu"="hexagonv65" }
48