1; RUN: llc -march=hexagon < %s | FileCheck %s
2
3@c = external global <32 x i32>
4@d = external global <16 x i32>
5
6; CHECK-LABEL: test1:
7; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.b,r{{[0-9]+}}.b)
8define void @test1(<32 x i32> %a, i32 %b) #0 {
9entry:
10  %0 = load <32 x i32>, <32 x i32>* @c, align 128
11  %1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
12  store <32 x i32> %1, <32 x i32>* @c, align 128
13  ret void
14}
15
16; CHECK-LABEL: test2:
17; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
18define void @test2(<32 x i32> %a, i32 %b) #0 {
19entry:
20  %0 = load <32 x i32>, <32 x i32>* @c, align 128
21  %1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpybus.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
22  store <32 x i32> %1, <32 x i32>* @c, align 128
23  ret void
24}
25
26; CHECK-LABEL: test3:
27; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vtmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
28define void @test3(<32 x i32> %a, i32 %b) #0 {
29entry:
30  %0 = load <32 x i32>, <32 x i32>* @c, align 128
31  %1 = tail call <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
32  store <32 x i32> %1, <32 x i32>* @c, align 128
33  ret void
34}
35
36; CHECK-LABEL: test4:
37; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.b)
38define void @test4(<16 x i32> %a, i32 %b) #0 {
39entry:
40  %0 = load <16 x i32>, <16 x i32>* @d, align 64
41  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
42  store <16 x i32> %1, <16 x i32>* @d, align 64
43  ret void
44}
45
46; CHECK-LABEL: test5:
47; CHECK: v{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)
48define void @test5(<16 x i32> %a, i32 %b) #0 {
49entry:
50  %0 = load <16 x i32>, <16 x i32>* @d, align 64
51  %1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyub.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
52  store <16 x i32> %1, <16 x i32>* @d, align 64
53  ret void
54}
55
56; CHECK-LABEL: test6:
57; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
58define void @test6(<16 x i32> %a, i32 %b) #0 {
59entry:
60  %0 = load <16 x i32>, <16 x i32>* @d, align 64
61  %1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybus.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
62  store <16 x i32> %1, <16 x i32>* @d, align 64
63  ret void
64}
65
66; CHECK-LABEL: test7:
67; CHECK: v{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
68define void @test7(<16 x i32> %a, i32 %b) #0 {
69entry:
70  %0 = load <16 x i32>, <16 x i32>* @d, align 64
71  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
72  store <16 x i32> %1, <16 x i32>* @d, align 64
73  ret void
74}
75
76; CHECK-LABEL: test8:
77; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
78define void @test8(<32 x i32> %a, i32 %b) #0 {
79entry:
80  %0 = load <32 x i32>, <32 x i32>* @c, align 128
81  %1 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
82  store <32 x i32> %1, <32 x i32>* @c, align 128
83  ret void
84}
85
86; CHECK-LABEL: test9:
87; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.uh):sat
88define void @test9(<16 x i32> %a, i32 %b) #0 {
89entry:
90  %0 = load <16 x i32>, <16 x i32>* @d, align 64
91  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
92  store <16 x i32> %1, <16 x i32>* @d, align 64
93  ret void
94}
95
96; CHECK-LABEL: test10:
97; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.uh,#1):sat
98define void @test10(<32 x i32> %a, i32 %b) #0 {
99entry:
100  %0 = load <16 x i32>, <16 x i32>* @d, align 64
101  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc(<16 x i32> %0, <32 x i32> %a, i32 %b)
102  store <16 x i32> %1, <16 x i32>* @d, align 64
103  ret void
104}
105
106; CHECK-LABEL: test11:
107; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
108define void @test11(<32 x i32> %a, i32 %b) #0 {
109entry:
110  %0 = load <16 x i32>, <16 x i32>* @d, align 64
111  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhisat.acc(<16 x i32> %0, <32 x i32> %a, i32 %b)
112  store <16 x i32> %1, <16 x i32>* @d, align 64
113  ret void
114}
115
116; CHECK-LABEL: test12:
117; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
118define void @test12(<16 x i32> %a, i32 %b) #0 {
119entry:
120  %0 = load <16 x i32>, <16 x i32>* @d, align 64
121  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhsat.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
122  store <16 x i32> %1, <16 x i32>* @d, align 64
123  ret void
124}
125
126; CHECK-LABEL: test13:
127; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
128define void @test13(<32 x i32> %a, i32 %b) #0 {
129entry:
130  %0 = load <32 x i32>, <32 x i32>* @c, align 128
131  %1 = tail call <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
132  store <32 x i32> %1, <32 x i32>* @c, align 128
133  ret void
134}
135
136; CHECK-LABEL: test14:
137; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.b)
138define void @test14(<16 x i32> %a, i32 %b) #0 {
139entry:
140  %0 = load <32 x i32>, <32 x i32>* @c, align 128
141  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
142  store <32 x i32> %1, <32 x i32>* @c, align 128
143  ret void
144}
145
146; CHECK-LABEL: test15:
147; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpa(v{{[0-9]+}}:{{[0-9]+}}.ub,r{{[0-9]+}}.b)
148define void @test15(<32 x i32> %a, i32 %b) #0 {
149entry:
150  %0 = load <32 x i32>, <32 x i32>* @c, align 128
151  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
152  store <32 x i32> %1, <32 x i32>* @c, align 128
153  ret void
154}
155
156; CHECK-LABEL: test16:
157; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpa(v{{[0-9]+}}:{{[0-9]+}}.h,r{{[0-9]+}}.b)
158define void @test16(<32 x i32> %a, i32 %b) #0 {
159entry:
160  %0 = load <32 x i32>, <32 x i32>* @c, align 128
161  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
162  store <32 x i32> %1, <32 x i32>* @c, align 128
163  ret void
164}
165
166; CHECK-LABEL: test17:
167; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,r{{[0-9]+}}.h):sat
168define void @test17(<16 x i32> %a, i32 %b) #0 {
169entry:
170  %0 = load <32 x i32>, <32 x i32>* @c, align 128
171  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
172  store <32 x i32> %1, <32 x i32>* @c, align 128
173  ret void
174}
175
176; CHECK-LABEL: test18:
177; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vmpy(v{{[0-9]+}}.uh,r{{[0-9]+}}.uh)
178define void @test18(<16 x i32> %a, i32 %b) #0 {
179entry:
180  %0 = load <32 x i32>, <32 x i32>* @c, align 128
181  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuh.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
182  store <32 x i32> %1, <32 x i32>* @c, align 128
183  ret void
184}
185
186; CHECK-LABEL: test19:
187; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.b)
188define void @test19(<16 x i32> %a, i32 %b) #0 {
189entry:
190  %0 = load <16 x i32>, <16 x i32>* @d, align 64
191  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
192  store <16 x i32> %1, <16 x i32>* @d, align 64
193  ret void
194}
195
196; CHECK-LABEL: test20:
197; CHECK: v{{[0-9]+}}.w += vmpyi(v{{[0-9]+}}.w,r{{[0-9]+}}.h)
198define void @test20(<16 x i32> %a, i32 %b) #0 {
199entry:
200  %0 = load <16 x i32>, <16 x i32>* @d, align 64
201  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
202  store <16 x i32> %1, <16 x i32>* @d, align 64
203  ret void
204}
205
206; CHECK-LABEL: test21:
207; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vdsad(v{{[0-9]+}}:{{[0-9]+}}.uh,r{{[0-9]+}}.uh)
208define void @test21(<32 x i32> %a, i32 %b) #0 {
209entry:
210  %0 = load <32 x i32>, <32 x i32>* @c, align 128
211  %1 = tail call <32 x i32> @llvm.hexagon.V6.vdsaduh.acc(<32 x i32> %0, <32 x i32> %a, i32 %b)
212  store <32 x i32> %1, <32 x i32>* @c, align 128
213  ret void
214}
215
216; CHECK-LABEL: test22:
217; CHECK: v{{[0-9]+}}.h += vmpyi(v{{[0-9]+}}.h,r{{[0-9]+}}.b)
218define void @test22(<16 x i32> %a, i32 %b) #0 {
219entry:
220  %0 = load <16 x i32>, <16 x i32>* @d, align 64
221  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyihb.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
222  store <16 x i32> %1, <16 x i32>* @d, align 64
223  ret void
224}
225
226; CHECK-LABEL: test23:
227; CHECK: v{{[0-9]+}}.w += vasl(v{{[0-9]+}}.w,r{{[0-9]+}})
228define void @test23(<16 x i32> %a, i32 %b) #0 {
229entry:
230  %0 = load <16 x i32>, <16 x i32>* @d, align 64
231  %1 = tail call <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
232  store <16 x i32> %1, <16 x i32>* @d, align 64
233  ret void
234}
235
236; CHECK-LABEL: test24:
237; CHECK: v{{[0-9]+}}.w += vasr(v{{[0-9]+}}.w,r{{[0-9]+}})
238define void @test24(<16 x i32> %a, i32 %b) #0 {
239entry:
240  %0 = load <16 x i32>, <16 x i32>* @d, align 64
241  %1 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %0, <16 x i32> %a, i32 %b)
242  store <16 x i32> %1, <16 x i32>* @d, align 64
243  ret void
244}
245
246; CHECK-LABEL: test25:
247; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh += vmpy(v{{[0-9]+}}.ub,r{{[0-9]+}}.ub)
248define void @test25(<16 x i32> %a, i32 %b) #0 {
249entry:
250  %0 = load <32 x i32>, <32 x i32>* @c, align 128
251  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyub.acc(<32 x i32> %0, <16 x i32> %a, i32 %b)
252  store <32 x i32> %1, <32 x i32>* @c, align 128
253  ret void
254}
255
256; CHECK-LABEL: test26:
257; CHECK: v{{[0-9]+}}.w += vdmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h):sat
258define void @test26(<16 x i32> %a, <16 x i32> %b) #0 {
259entry:
260  %0 = load <16 x i32>, <16 x i32>* @d, align 64
261  %1 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
262  store <16 x i32> %1, <16 x i32>* @d, align 64
263  ret void
264}
265
266; CHECK-LABEL: test27:
267; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)
268define void @test27(<16 x i32> %a, <16 x i32> %b) #0 {
269entry:
270  %0 = load <32 x i32>, <32 x i32>* @c, align 128
271  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybusv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
272  store <32 x i32> %1, <32 x i32>* @c, align 128
273  ret void
274}
275
276; CHECK-LABEL: test28:
277; CHECK: v{{[0-9]+}}:{{[0-9]+}}.h += vmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
278define void @test28(<16 x i32> %a, <16 x i32> %b) #0 {
279entry:
280  %0 = load <32 x i32>, <32 x i32>* @c, align 128
281  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpybv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
282  store <32 x i32> %1, <32 x i32>* @c, align 128
283  ret void
284}
285
286; CHECK-LABEL: test29:
287; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.uh)
288define void @test29(<16 x i32> %a, <16 x i32> %b) #0 {
289entry:
290  %0 = load <32 x i32>, <32 x i32>* @c, align 128
291  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhus.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
292  store <32 x i32> %1, <32 x i32>* @c, align 128
293  ret void
294}
295
296; CHECK-LABEL: test30:
297; CHECK: v{{[0-9]+}}:{{[0-9]+}}.w += vmpy(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
298define void @test30(<16 x i32> %a, <16 x i32> %b) #0 {
299entry:
300  %0 = load <32 x i32>, <32 x i32>* @c, align 128
301  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyhv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
302  store <32 x i32> %1, <32 x i32>* @c, align 128
303  ret void
304}
305
306; CHECK-LABEL: test31:
307; CHECK: v{{[0-9]+}}.w += vmpyie(v{{[0-9]+}}.w,v{{[0-9]+}}.h)
308define void @test31(<16 x i32> %a, <16 x i32> %b) #0 {
309entry:
310  %0 = load <16 x i32>, <16 x i32>* @d, align 64
311  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewh.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
312  store <16 x i32> %1, <16 x i32>* @d, align 64
313  ret void
314}
315
316; CHECK-LABEL: test32:
317; CHECK: v{{[0-9]+}}.w += vmpyie(v{{[0-9]+}}.w,v{{[0-9]+}}.uh)
318define void @test32(<16 x i32> %a, <16 x i32> %b) #0 {
319entry:
320  %0 = load <16 x i32>, <16 x i32>* @d, align 64
321  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
322  store <16 x i32> %1, <16 x i32>* @d, align 64
323  ret void
324}
325
326; CHECK-LABEL: test33:
327; CHECK: v{{[0-9]+}}.h += vmpyi(v{{[0-9]+}}.h,v{{[0-9]+}}.h)
328define void @test33(<16 x i32> %a, <16 x i32> %b) #0 {
329entry:
330  %0 = load <16 x i32>, <16 x i32>* @d, align 64
331  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyih.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
332  store <16 x i32> %1, <16 x i32>* @d, align 64
333  ret void
334}
335
336; CHECK-LABEL: test34:
337; CHECK: v{{[0-9]+}}.w += vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:rnd:sat:shift
338define void @test34(<16 x i32> %a, <16 x i32> %b) #0 {
339entry:
340  %0 = load <16 x i32>, <16 x i32>* @d, align 64
341  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd.sacc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
342  store <16 x i32> %1, <16 x i32>* @d, align 64
343  ret void
344}
345
346; CHECK-LABEL: test35:
347; CHECK: v{{[0-9]+}}.w += vmpyo(v{{[0-9]+}}.w,v{{[0-9]+}}.h):<<1:sat:shift
348define void @test35(<16 x i32> %a, <16 x i32> %b) #0 {
349entry:
350  %0 = load <16 x i32>, <16 x i32>* @d, align 64
351  %1 = tail call <16 x i32> @llvm.hexagon.V6.vmpyowh.sacc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
352  store <16 x i32> %1, <16 x i32>* @d, align 64
353  ret void
354}
355
356; CHECK-LABEL: test36:
357; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uh += vmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
358define void @test36(<16 x i32> %a, <16 x i32> %b) #0 {
359entry:
360  %0 = load <32 x i32>, <32 x i32>* @c, align 128
361  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyubv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
362  store <32 x i32> %1, <32 x i32>* @c, align 128
363  ret void
364}
365
366; CHECK-LABEL: test37:
367; CHECK: v{{[0-9]+}}:{{[0-9]+}}.uw += vmpy(v{{[0-9]+}}.uh,v{{[0-9]+}}.uh)
368define void @test37(<16 x i32> %a, <16 x i32> %b) #0 {
369entry:
370  %0 = load <32 x i32>, <32 x i32>* @c, align 128
371  %1 = tail call <32 x i32> @llvm.hexagon.V6.vmpyuhv.acc(<32 x i32> %0, <16 x i32> %a, <16 x i32> %b)
372  store <32 x i32> %1, <32 x i32>* @c, align 128
373  ret void
374}
375
376; CHECK-LABEL: test38:
377; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.b)
378define void @test38(<16 x i32> %a, <16 x i32> %b) #0 {
379entry:
380  %0 = load <16 x i32>, <16 x i32>* @d, align 64
381  %1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybusv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
382  store <16 x i32> %1, <16 x i32>* @d, align 64
383  ret void
384}
385
386; CHECK-LABEL: test39:
387; CHECK: v{{[0-9]+}}.w += vrmpy(v{{[0-9]+}}.b,v{{[0-9]+}}.b)
388define void @test39(<16 x i32> %a, <16 x i32> %b) #0 {
389entry:
390  %0 = load <16 x i32>, <16 x i32>* @d, align 64
391  %1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpybv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
392  store <16 x i32> %1, <16 x i32>* @d, align 64
393  ret void
394}
395
396; CHECK-LABEL: test40:
397; CHECK: v{{[0-9]+}}.uw += vrmpy(v{{[0-9]+}}.ub,v{{[0-9]+}}.ub)
398define void @test40(<16 x i32> %a, <16 x i32> %b) #0 {
399entry:
400  %0 = load <16 x i32>, <16 x i32>* @d, align 64
401  %1 = tail call <16 x i32> @llvm.hexagon.V6.vrmpyubv.acc(<16 x i32> %0, <16 x i32> %a, <16 x i32> %b)
402  store <16 x i32> %1, <16 x i32>* @d, align 64
403  ret void
404}
405
406declare <32 x i32> @llvm.hexagon.V6.vtmpyb.acc(<32 x i32>, <32 x i32>, i32) #0
407declare <32 x i32> @llvm.hexagon.V6.vtmpybus.acc(<32 x i32>, <32 x i32>, i32) #0
408declare <32 x i32> @llvm.hexagon.V6.vtmpyhb.acc(<32 x i32>, <32 x i32>, i32) #0
409declare <16 x i32> @llvm.hexagon.V6.vdmpyhb.acc(<16 x i32>, <16 x i32>, i32) #0
410declare <16 x i32> @llvm.hexagon.V6.vrmpyub.acc(<16 x i32>, <16 x i32>, i32) #0
411declare <16 x i32> @llvm.hexagon.V6.vrmpybus.acc(<16 x i32>, <16 x i32>, i32) #0
412declare <16 x i32> @llvm.hexagon.V6.vdmpybus.acc(<16 x i32>, <16 x i32>, i32) #0
413declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #0
414declare <16 x i32> @llvm.hexagon.V6.vdmpyhsusat.acc(<16 x i32>, <16 x i32>, i32) #0
415declare <16 x i32> @llvm.hexagon.V6.vdmpyhsuisat.acc(<16 x i32>, <32 x i32>, i32) #0
416declare <16 x i32> @llvm.hexagon.V6.vdmpyhisat.acc(<16 x i32>, <32 x i32>, i32) #0
417declare <16 x i32> @llvm.hexagon.V6.vdmpyhsat.acc(<16 x i32>, <16 x i32>, i32) #0
418declare <32 x i32> @llvm.hexagon.V6.vdmpyhb.dv.acc(<32 x i32>, <32 x i32>, i32) #0
419declare <32 x i32> @llvm.hexagon.V6.vmpybus.acc(<32 x i32>, <16 x i32>, i32) #0
420declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0
421declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0
422declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0
423declare <32 x i32> @llvm.hexagon.V6.vmpyuh.acc(<32 x i32>, <16 x i32>, i32) #0
424declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
425declare <16 x i32> @llvm.hexagon.V6.vmpyiwh.acc(<16 x i32>, <16 x i32>, i32) #0
426declare <32 x i32> @llvm.hexagon.V6.vdsaduh.acc(<32 x i32>, <32 x i32>, i32) #0
427declare <16 x i32> @llvm.hexagon.V6.vmpyihb.acc(<16 x i32>, <16 x i32>, i32) #0
428declare <16 x i32> @llvm.hexagon.V6.vaslw.acc(<16 x i32>, <16 x i32>, i32) #0
429declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #0
430declare <32 x i32> @llvm.hexagon.V6.vmpyub.acc(<32 x i32>, <16 x i32>, i32) #0
431declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
432declare <32 x i32> @llvm.hexagon.V6.vmpybusv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
433declare <32 x i32> @llvm.hexagon.V6.vmpybv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
434declare <32 x i32> @llvm.hexagon.V6.vmpyhus.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
435declare <32 x i32> @llvm.hexagon.V6.vmpyhv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
436declare <16 x i32> @llvm.hexagon.V6.vmpyiewh.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
437declare <16 x i32> @llvm.hexagon.V6.vmpyiewuh.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
438declare <16 x i32> @llvm.hexagon.V6.vmpyih.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
439declare <16 x i32> @llvm.hexagon.V6.vmpyowh.rnd.sacc(<16 x i32>, <16 x i32>, <16 x i32>) #0
440declare <16 x i32> @llvm.hexagon.V6.vmpyowh.sacc(<16 x i32>, <16 x i32>, <16 x i32>) #0
441declare <32 x i32> @llvm.hexagon.V6.vmpyubv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
442declare <32 x i32> @llvm.hexagon.V6.vmpyuhv.acc(<32 x i32>, <16 x i32>, <16 x i32>) #0
443declare <16 x i32> @llvm.hexagon.V6.vrmpybusv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
444declare <16 x i32> @llvm.hexagon.V6.vrmpybv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
445declare <16 x i32> @llvm.hexagon.V6.vrmpyubv.acc(<16 x i32>, <16 x i32>, <16 x i32>) #0
446
447attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx60,+hvx-length64b" }
448