1; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s
2; REQUIRES: asserts
3
4; This test validates that ISel picks the correct equivalent of below mentioned intrinsics
5; For S2_asr_i_r_rnd_goodsyntax:
6;   if (#u5 == 0) Assembler mapped to: Rd = Rs
7;   else Rd = asr(Rs,#u5-1):rnd
8; For S2_asr_i_p_rnd_goodsyntax:
9;   if (#u6 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)
10;   else Rdd = asr(Rss,#u6-1):rnd
11; For S5_vasrhrnd_goodsyntax:
12;   if (#u4 == 0) Assembler mapped to: Rdd = combine(Rss.H32,Rss.L32)
13;   else Rdd = vasrh(Rss,#u4-1):raw
14; For S5_asrhub_rnd_sat_goodsyntax:
15;   if (#u4 == 0) Assembler mapped to: Rd = vsathub(Rss)
16;   else Rd = vasrhub(Rss,#u4-1):raw
17
18target triple = "hexagon-unknown--elf"
19
20; CHECK-LABEL: f0
21; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
22; CHECK: Morphed node{{.*}}A2_tfr
23define i32 @f0(i32 %a0, i32 %a1) local_unnamed_addr #0 {
24b0:
25  %v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 0)
26  %v1 = add i32 %v0, %a1
27  ret i32 %v1
28}
29
30declare i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32, i32) #1
31
32; CHECK-LABEL: f1
33; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.r.rnd.goodsyntax
34; CHECK: Morphed node{{.*}}S2_asr_i_r_rnd
35define i32 @f1(i32 %a0, i32 %a1) local_unnamed_addr #0 {
36b0:
37  %v0 = tail call i32 @llvm.hexagon.S2.asr.i.r.rnd.goodsyntax(i32 %a0, i32 9)
38  %v1 = add i32 %v0, %a1
39  ret i32 %v1
40}
41
42; CHECK-LABEL: f2
43; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
44; CHECK: Morphed node{{.*}}A2_combinew
45define i64 @f2(i64 %a0, i32 %a1) local_unnamed_addr #0 {
46b0:
47  %v0 = zext i32 %a1 to i64
48  %v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 0)
49  %v2 = add nsw i64 %v1, %v0
50  ret i64 %v2
51}
52
53declare i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64, i32) #1
54
55; CHECK-LABEL: f3
56; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S2.asr.i.p.rnd.goodsyntax
57; CHECK: Morphed node{{.*}}S2_asr_i_p_rnd
58define i64 @f3(i64 %a0, i32 %a1) local_unnamed_addr #0 {
59b0:
60  %v0 = zext i32 %a1 to i64
61  %v1 = tail call i64 @llvm.hexagon.S2.asr.i.p.rnd.goodsyntax(i64 %a0, i32 9)
62  %v2 = add nsw i64 %v1, %v0
63  ret i64 %v2
64}
65
66; CHECK-LABEL: f4
67; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
68; CHECK: Morphed node{{.*}}S2_vsathub
69define i32 @f4(i64 %a0, i32 %a1) local_unnamed_addr #0 {
70b0:
71  %v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 0)
72  %v1 = add i32 %v0, %a1
73  ret i32 %v1
74}
75
76declare i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64, i32) #1
77
78; CHECK-LABEL: f5
79; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax
80; CHECK: Morphed node{{.*}}S5_asrhub_rnd_sat
81define i32 @f5(i64 %a0, i32 %a1) local_unnamed_addr #0 {
82b0:
83  %v0 = tail call i32 @llvm.hexagon.S5.asrhub.rnd.sat.goodsyntax(i64 %a0, i32 9)
84  %v1 = add i32 %v0, %a1
85  ret i32 %v1
86}
87
88; CHECK-LABEL: f6
89; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
90; CHECK: Morphed node{{.*}}A2_combinew
91define i64 @f6(i64 %a0, i32 %a1) local_unnamed_addr #0 {
92b0:
93  %v0 = zext i32 %a1 to i64
94  %v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 0)
95  %v2 = add nsw i64 %v1, %v0
96  ret i64 %v2
97}
98
99declare i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64, i32) #1
100
101; CHECK-LABEL: f7
102; CHECK: ISEL: Starting selection on{{.*}}llvm.hexagon.S5.vasrhrnd.goodsyntax
103; CHECK: Morphed node{{.*}}S5_vasrhrnd
104define i64 @f7(i64 %a0, i32 %a1) local_unnamed_addr #0 {
105b0:
106  %v0 = zext i32 %a1 to i64
107  %v1 = tail call i64 @llvm.hexagon.S5.vasrhrnd.goodsyntax(i64 %a0, i32 9)
108  %v2 = add nsw i64 %v1, %v0
109  ret i64 %v2
110}
111
112attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }
113attributes #1 = { nounwind readnone }
114