1; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s | FileCheck %s
2
3; Test that we generate the correct phi names in the epilog when the pipeliner
4; schedules a phi and it's loop definition in different stages, e.g., a phi is
5; scheduled in stage 2, but the loop definition in scheduled in stage 0). The
6; code in generateExistingPhis was generating the wrong name for the last
7; epilog bock.
8
9; CHECK: endloop0
10; CHECK: sub([[REG:r([0-9]+)]],r{{[0-9]+}}):sat
11; CHECK-NOT: sub([[REG]],r{{[0-9]+}}):sat
12
13define void @f0() {
14b0:
15  br label %b1
16
17b1:                                               ; preds = %b1, %b0
18  br i1 undef, label %b2, label %b1
19
20b2:                                               ; preds = %b1
21  br label %b3
22
23b3:                                               ; preds = %b3, %b2
24  %v0 = phi i32 [ %v8, %b3 ], [ 7, %b2 ]
25  %v1 = phi i32 [ %v6, %b3 ], [ undef, %b2 ]
26  %v2 = phi i32 [ %v1, %b3 ], [ undef, %b2 ]
27  %v3 = getelementptr inbounds [9 x i32], [9 x i32]* undef, i32 0, i32 %v0
28  %v4 = add nsw i32 %v0, -2
29  %v5 = getelementptr inbounds [9 x i32], [9 x i32]* undef, i32 0, i32 %v4
30  %v6 = load i32, i32* %v5, align 4
31  %v7 = tail call i32 @llvm.hexagon.A2.subsat(i32 %v2, i32 %v6)
32  store i32 %v7, i32* %v3, align 4
33  %v8 = add i32 %v0, -1
34  %v9 = icmp sgt i32 %v8, 1
35  br i1 %v9, label %b3, label %b4
36
37b4:                                               ; preds = %b3
38  unreachable
39}
40
41; Function Attrs: nounwind readnone
42declare i32 @llvm.hexagon.A2.subsat(i32, i32) #0
43
44attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }
45