1; RUN: llc -march=hexagon -O2 < %s
2; REQUIRES: asserts
3
4; Test that we generate the correct Phi names in the epilog when we need
5; to reuse an existing Phi. This bug caused an assert in live variable
6; analysis because the wrong virtual register was used.
7; The bug occurs when a Phi references another Phi, and referent Phi
8; value is used in multiple stages. When this occurs, the referring Phi
9; can reuse one of the new values. We have code that deals with this in the
10; kernel, but this case can occur in the epilog too.
11
12; Function Attrs: nounwind readnone
13declare <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32>, <16 x i32>) #0
14
15; Function Attrs: nounwind readnone
16declare <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32>, <32 x i32>, i32) #0
17
18; Function Attrs: nounwind readnone
19declare <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32>, <16 x i32>, i32) #0
20
21; Function Attrs: nounwind readnone
22declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #0
23
24; Function Attrs: nounwind readnone
25declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #0
26
27; Function Attrs: nounwind readnone
28declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #0
29
30; Function Attrs: nounwind readnone
31declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #0
32
33; Function Attrs: nounwind readnone
34declare <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32>, <16 x i32>, i32) #0
35
36; Function Attrs: nounwind readnone
37declare <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32>, <16 x i32>) #0
38
39; Function Attrs: nounwind
40define void @f0(i8* noalias nocapture readonly %a0, i32 %a1, i32 %a2) #1 {
41b0:
42  %v0 = mul nsw i32 %a1, 2
43  br i1 undef, label %b1, label %b5
44
45b1:                                               ; preds = %b0
46  %v1 = getelementptr inbounds i8, i8* %a0, i32 %v0
47  %v2 = icmp sgt i32 %a2, 64
48  %v3 = add i32 %v0, 64
49  %v4 = add i32 %a1, 64
50  %v5 = sub i32 64, %a1
51  %v6 = sub i32 64, %v0
52  br i1 %v2, label %b2, label %b4
53
54b2:                                               ; preds = %b1
55  %v7 = getelementptr inbounds i8, i8* %v1, i32 %v3
56  %v8 = getelementptr inbounds i8, i8* %v1, i32 %v4
57  %v9 = getelementptr inbounds i8, i8* %v1, i32 64
58  %v10 = getelementptr inbounds i8, i8* %v1, i32 %v5
59  %v11 = getelementptr inbounds i8, i8* %v1, i32 %v6
60  %v12 = bitcast i8* %v7 to <16 x i32>*
61  %v13 = bitcast i8* %v8 to <16 x i32>*
62  %v14 = bitcast i8* %v9 to <16 x i32>*
63  %v15 = bitcast i8* %v10 to <16 x i32>*
64  %v16 = bitcast i8* %v11 to <16 x i32>*
65  br label %b3
66
67b3:                                               ; preds = %b3, %b2
68  %v17 = phi <16 x i32>* [ null, %b2 ], [ %v52, %b3 ]
69  %v18 = phi <16 x i32>* [ %v12, %b2 ], [ %v34, %b3 ]
70  %v19 = phi <16 x i32>* [ %v13, %b2 ], [ %v32, %b3 ]
71  %v20 = phi <16 x i32>* [ %v14, %b2 ], [ %v30, %b3 ]
72  %v21 = phi <16 x i32>* [ %v15, %b2 ], [ %v28, %b3 ]
73  %v22 = phi <16 x i32>* [ %v16, %b2 ], [ %v26, %b3 ]
74  %v23 = phi <32 x i32> [ undef, %b2 ], [ %v37, %b3 ]
75  %v24 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v23, %b3 ]
76  %v25 = phi i32 [ %a2, %b2 ], [ %v53, %b3 ]
77  %v26 = getelementptr inbounds <16 x i32>, <16 x i32>* %v22, i32 1
78  %v27 = load <16 x i32>, <16 x i32>* %v22, align 64
79  %v28 = getelementptr inbounds <16 x i32>, <16 x i32>* %v21, i32 1
80  %v29 = load <16 x i32>, <16 x i32>* %v21, align 64
81  %v30 = getelementptr inbounds <16 x i32>, <16 x i32>* %v20, i32 1
82  %v31 = load <16 x i32>, <16 x i32>* %v20, align 64
83  %v32 = getelementptr inbounds <16 x i32>, <16 x i32>* %v19, i32 1
84  %v33 = load <16 x i32>, <16 x i32>* %v19, align 64
85  %v34 = getelementptr inbounds <16 x i32>, <16 x i32>* %v18, i32 1
86  %v35 = load <16 x i32>, <16 x i32>* %v18, align 64
87  %v36 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v33, <16 x i32> %v29) #3
88  %v37 = tail call <32 x i32> @llvm.hexagon.V6.vmpabus.acc(<32 x i32> undef, <32 x i32> %v36, i32 67372036) #3
89  %v38 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v23) #3
90  %v39 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v24) #3
91  %v40 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v38, <16 x i32> %v39, i32 2) #3
92  %v41 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v37) #3
93  %v42 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v41, <16 x i32> %v38, i32 2) #3
94  %v43 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v37) #3
95  %v44 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v43, <16 x i32> undef, i32 2) #3
96  %v45 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v40, <16 x i32> %v42) #3
97  %v46 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v45, <16 x i32> %v38, i32 101058054) #3
98  %v47 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v46, <16 x i32> zeroinitializer, i32 67372036) #3
99  %v48 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v44) #3
100  %v49 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v48, <16 x i32> undef, i32 101058054) #3
101  %v50 = tail call <16 x i32> @llvm.hexagon.V6.vmpyiwb.acc(<16 x i32> %v49, <16 x i32> zeroinitializer, i32 67372036) #3
102  %v51 = tail call <16 x i32> @llvm.hexagon.V6.vshuffob(<16 x i32> %v50, <16 x i32> %v47) #3
103  %v52 = getelementptr inbounds <16 x i32>, <16 x i32>* %v17, i32 1
104  store <16 x i32> %v51, <16 x i32>* %v17, align 64
105  %v53 = add nsw i32 %v25, -64
106  %v54 = icmp sgt i32 %v53, 64
107  br i1 %v54, label %b3, label %b4
108
109b4:                                               ; preds = %b3, %b1
110  unreachable
111
112b5:                                               ; preds = %b0
113  ret void
114}
115
116; Function Attrs: nounwind
117define void @f1(i32 %a0, i32* %a1) #1 {
118b0:
119  %v0 = ptrtoint i32* %a1 to i32
120  %v1 = ashr i32 %a0, 1
121  %v2 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 undef, i32 undef)
122  br i1 undef, label %b1, label %b2
123
124b1:                                               ; preds = %b1, %b0
125  br i1 undef, label %b1, label %b2
126
127b2:                                               ; preds = %b2, %b1, %b0
128  %v3 = phi i64 [ %v11, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
129  %v4 = phi i32 [ %v12, %b2 ], [ 0, %b0 ], [ undef, %b1 ]
130  %v5 = phi i32 [ %v6, %b2 ], [ %v2, %b0 ], [ undef, %b1 ]
131  %v6 = phi i32 [ %v10, %b2 ], [ undef, %b0 ], [ undef, %b1 ]
132  %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v3, i64 undef)
133  %v8 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v5, i32 %v5)
134  %v9 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 undef, i64 %v8, i64 undef)
135  %v10 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 0, i32 undef)
136  %v11 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v10, i32 %v6)
137  %v12 = add nsw i32 %v4, 1
138  %v13 = icmp eq i32 %v12, %v1
139  br i1 %v13, label %b3, label %b2
140
141b3:                                               ; preds = %b2
142  %v14 = phi i64 [ %v9, %b2 ]
143  %v15 = phi i64 [ %v7, %b2 ]
144  %v16 = trunc i64 %v14 to i32
145  %v17 = trunc i64 %v15 to i32
146  %v18 = inttoptr i32 %v0 to i32*
147  store i32 %v17, i32* %v18, align 4
148  %v19 = bitcast i8* undef to i32*
149  store i32 %v16, i32* %v19, align 4
150  call void @llvm.trap()
151  unreachable
152}
153
154; Function Attrs: nounwind readnone
155declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #0
156
157; Function Attrs: nounwind readnone
158declare i64 @llvm.hexagon.A2.combinew(i32, i32) #0
159
160; Function Attrs: nounwind readnone
161declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #0
162
163; Function Attrs: noreturn nounwind
164declare void @llvm.trap() #2
165
166attributes #0 = { nounwind readnone }
167attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
168attributes #2 = { noreturn nounwind }
169attributes #3 = { nounwind }
170