1; RUN: llc -march=hexagon -O0 < %s | FileCheck %s
2; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
3
4; CHECK: v{{[0-9]*}} = vxor(v{{[0-9]*}},v{{[0-9]*}})
5; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b
6; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b
7; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h
8; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h
9; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w
10; CHECK: if (q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w
11; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b += v{{[0-9]*}}.b
12; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.b -= v{{[0-9]*}}.b
13; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h += v{{[0-9]*}}.h
14; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.h -= v{{[0-9]*}}.h
15; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w += v{{[0-9]*}}.w
16; CHECK: if (!q{{[-0-3]}}) v{{[0-9]*}}.w -= v{{[0-9]*}}.w
17
18target triple = "hexagon"
19
20@g0 = common global <16 x i32> zeroinitializer, align 64
21@g1 = common global <16 x i32> zeroinitializer, align 64
22@g2 = common global <16 x i32> zeroinitializer, align 64
23@g3 = common global <16 x i32> zeroinitializer, align 64
24
25; Function Attrs: nounwind
26define i32 @f0() #0 {
27b0:
28  %v0 = call <16 x i32> @llvm.hexagon.V6.vd0()
29  store <16 x i32> %v0, <16 x i32>* @g0, align 64
30  %v1 = call <16 x i32> @llvm.hexagon.V6.vd0()
31  store <16 x i32> %v1, <16 x i32>* @g1, align 64
32  %v2 = call <16 x i32> @llvm.hexagon.V6.vd0()
33  store <16 x i32> %v2, <16 x i32>* @g2, align 64
34  %v3 = load <16 x i32>, <16 x i32>* @g3, align 64
35  %v4 = bitcast <16 x i32> %v3 to <512 x i1>
36  %v5 = load <16 x i32>, <16 x i32>* @g2, align 64
37  %v6 = load <16 x i32>, <16 x i32>* @g1, align 64
38  %v7 = call <16 x i32> @llvm.hexagon.V6.vaddbq(<512 x i1> %v4, <16 x i32> %v5, <16 x i32> %v6)
39  store <16 x i32> %v7, <16 x i32>* @g2, align 64
40  %v8 = load <16 x i32>, <16 x i32>* @g3, align 64
41  %v9 = bitcast <16 x i32> %v8 to <512 x i1>
42  %v10 = load <16 x i32>, <16 x i32>* @g2, align 64
43  %v11 = load <16 x i32>, <16 x i32>* @g1, align 64
44  %v12 = call <16 x i32> @llvm.hexagon.V6.vsubbq(<512 x i1> %v9, <16 x i32> %v10, <16 x i32> %v11)
45  store <16 x i32> %v12, <16 x i32>* @g2, align 64
46  %v13 = load <16 x i32>, <16 x i32>* @g3, align 64
47  %v14 = bitcast <16 x i32> %v13 to <512 x i1>
48  %v15 = load <16 x i32>, <16 x i32>* @g2, align 64
49  %v16 = load <16 x i32>, <16 x i32>* @g1, align 64
50  %v17 = call <16 x i32> @llvm.hexagon.V6.vaddhq(<512 x i1> %v14, <16 x i32> %v15, <16 x i32> %v16)
51  store <16 x i32> %v17, <16 x i32>* @g2, align 64
52  %v18 = load <16 x i32>, <16 x i32>* @g3, align 64
53  %v19 = bitcast <16 x i32> %v18 to <512 x i1>
54  %v20 = load <16 x i32>, <16 x i32>* @g2, align 64
55  %v21 = load <16 x i32>, <16 x i32>* @g1, align 64
56  %v22 = call <16 x i32> @llvm.hexagon.V6.vsubhq(<512 x i1> %v19, <16 x i32> %v20, <16 x i32> %v21)
57  store <16 x i32> %v22, <16 x i32>* @g2, align 64
58  %v23 = load <16 x i32>, <16 x i32>* @g3, align 64
59  %v24 = bitcast <16 x i32> %v23 to <512 x i1>
60  %v25 = load <16 x i32>, <16 x i32>* @g2, align 64
61  %v26 = load <16 x i32>, <16 x i32>* @g1, align 64
62  %v27 = call <16 x i32> @llvm.hexagon.V6.vaddwq(<512 x i1> %v24, <16 x i32> %v25, <16 x i32> %v26)
63  store <16 x i32> %v27, <16 x i32>* @g2, align 64
64  %v28 = load <16 x i32>, <16 x i32>* @g3, align 64
65  %v29 = bitcast <16 x i32> %v28 to <512 x i1>
66  %v30 = load <16 x i32>, <16 x i32>* @g2, align 64
67  %v31 = load <16 x i32>, <16 x i32>* @g1, align 64
68  %v32 = call <16 x i32> @llvm.hexagon.V6.vsubwq(<512 x i1> %v29, <16 x i32> %v30, <16 x i32> %v31)
69  store <16 x i32> %v32, <16 x i32>* @g2, align 64
70  %v33 = load <16 x i32>, <16 x i32>* @g3, align 64
71  %v34 = bitcast <16 x i32> %v33 to <512 x i1>
72  %v35 = load <16 x i32>, <16 x i32>* @g2, align 64
73  %v36 = load <16 x i32>, <16 x i32>* @g1, align 64
74  %v37 = call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v34, <16 x i32> %v35, <16 x i32> %v36)
75  store <16 x i32> %v37, <16 x i32>* @g2, align 64
76  %v38 = load <16 x i32>, <16 x i32>* @g3, align 64
77  %v39 = bitcast <16 x i32> %v38 to <512 x i1>
78  %v40 = load <16 x i32>, <16 x i32>* @g2, align 64
79  %v41 = load <16 x i32>, <16 x i32>* @g1, align 64
80  %v42 = call <16 x i32> @llvm.hexagon.V6.vsubbnq(<512 x i1> %v39, <16 x i32> %v40, <16 x i32> %v41)
81  store <16 x i32> %v42, <16 x i32>* @g2, align 64
82  %v43 = load <16 x i32>, <16 x i32>* @g3, align 64
83  %v44 = bitcast <16 x i32> %v43 to <512 x i1>
84  %v45 = load <16 x i32>, <16 x i32>* @g2, align 64
85  %v46 = load <16 x i32>, <16 x i32>* @g1, align 64
86  %v47 = call <16 x i32> @llvm.hexagon.V6.vaddhnq(<512 x i1> %v44, <16 x i32> %v45, <16 x i32> %v46)
87  store <16 x i32> %v47, <16 x i32>* @g2, align 64
88  %v48 = load <16 x i32>, <16 x i32>* @g3, align 64
89  %v49 = bitcast <16 x i32> %v48 to <512 x i1>
90  %v50 = load <16 x i32>, <16 x i32>* @g2, align 64
91  %v51 = load <16 x i32>, <16 x i32>* @g1, align 64
92  %v52 = call <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1> %v49, <16 x i32> %v50, <16 x i32> %v51)
93  store <16 x i32> %v52, <16 x i32>* @g2, align 64
94  %v53 = load <16 x i32>, <16 x i32>* @g3, align 64
95  %v54 = bitcast <16 x i32> %v53 to <512 x i1>
96  %v55 = load <16 x i32>, <16 x i32>* @g2, align 64
97  %v56 = load <16 x i32>, <16 x i32>* @g1, align 64
98  %v57 = call <16 x i32> @llvm.hexagon.V6.vaddwnq(<512 x i1> %v54, <16 x i32> %v55, <16 x i32> %v56)
99  store <16 x i32> %v57, <16 x i32>* @g2, align 64
100  %v58 = load <16 x i32>, <16 x i32>* @g3, align 64
101  %v59 = bitcast <16 x i32> %v58 to <512 x i1>
102  %v60 = load <16 x i32>, <16 x i32>* @g2, align 64
103  %v61 = load <16 x i32>, <16 x i32>* @g1, align 64
104  %v62 = call <16 x i32> @llvm.hexagon.V6.vsubwnq(<512 x i1> %v59, <16 x i32> %v60, <16 x i32> %v61)
105  store <16 x i32> %v62, <16 x i32>* @g2, align 64
106  ret i32 0
107}
108
109; Function Attrs: nounwind readnone
110declare <16 x i32> @llvm.hexagon.V6.vd0() #1
111
112; Function Attrs: nounwind readnone
113declare <16 x i32> @llvm.hexagon.V6.vaddbq(<512 x i1>, <16 x i32>, <16 x i32>) #1
114
115; Function Attrs: nounwind readnone
116declare <16 x i32> @llvm.hexagon.V6.vsubbq(<512 x i1>, <16 x i32>, <16 x i32>) #1
117
118; Function Attrs: nounwind readnone
119declare <16 x i32> @llvm.hexagon.V6.vaddhq(<512 x i1>, <16 x i32>, <16 x i32>) #1
120
121; Function Attrs: nounwind readnone
122declare <16 x i32> @llvm.hexagon.V6.vsubhq(<512 x i1>, <16 x i32>, <16 x i32>) #1
123
124; Function Attrs: nounwind readnone
125declare <16 x i32> @llvm.hexagon.V6.vaddwq(<512 x i1>, <16 x i32>, <16 x i32>) #1
126
127; Function Attrs: nounwind readnone
128declare <16 x i32> @llvm.hexagon.V6.vsubwq(<512 x i1>, <16 x i32>, <16 x i32>) #1
129
130; Function Attrs: nounwind readnone
131declare <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
132
133; Function Attrs: nounwind readnone
134declare <16 x i32> @llvm.hexagon.V6.vsubbnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
135
136; Function Attrs: nounwind readnone
137declare <16 x i32> @llvm.hexagon.V6.vaddhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
138
139; Function Attrs: nounwind readnone
140declare <16 x i32> @llvm.hexagon.V6.vsubhnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
141
142; Function Attrs: nounwind readnone
143declare <16 x i32> @llvm.hexagon.V6.vaddwnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
144
145; Function Attrs: nounwind readnone
146declare <16 x i32> @llvm.hexagon.V6.vsubwnq(<512 x i1>, <16 x i32>, <16 x i32>) #1
147
148attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
149attributes #1 = { nounwind readnone }
150