1; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=MIPS32
2; RUN: llc  < %s -mtriple=mipsel-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=MM
3; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=MIPS64
4; RUN: llc  < %s -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips32r2 -mattr=+mips16 | FileCheck -allow-deprecated-dag-overlap %s -check-prefix=MIPS16
5
6define i32 @bswap32(i32 signext %x) nounwind readnone {
7entry:
8; MIPS32-LABEL: bswap32:
9; MIPS32: wsbh $[[R0:[0-9]+]]
10; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
11
12; MM-LABEL: bswap32:
13; MM: wsbh $[[R0:[0-9]+]]
14; MM: rotr ${{[0-9]+}}, $[[R0]], 16
15
16; MIPS64-LABEL: bswap32:
17; MIPS64: wsbh $[[R0:[0-9]+]]
18; MIPS64: rotr ${{[0-9]+}}, $[[R0]], 16
19
20; MIPS16-LABEL: bswap32:
21; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
22; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
23; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
24; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
25; MIPS16-DAG: li  $[[R4:[0-9]+]], 65280
26; MIPS16-DAG: and $[[R4]], $[[R0]]
27; MIPS16-DAG: or  $[[R1]], $[[R4]]
28; MIPS16-DAG: lw  $[[R7:[0-9]+]], $CPI
29; MIPS16-DAG: and $[[R7]], $[[R2]]
30; MIPS16-DAG: or  $[[R3]], $[[R7]]
31; MIPS16-DAG: or  $[[R3]], $[[R1]]
32
33  %or.3 = call i32 @llvm.bswap.i32(i32 %x)
34  ret i32 %or.3
35}
36
37define i64 @bswap64(i64 signext %x) nounwind readnone {
38entry:
39; MIPS32-LABEL: bswap64:
40; MIPS32: wsbh $[[R0:[0-9]+]]
41; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
42; MIPS32: wsbh $[[R0:[0-9]+]]
43; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
44
45; MM-LABEL: bswap64:
46; MM: wsbh $[[R0:[0-9]+]]
47; MM: rotr ${{[0-9]+}}, $[[R0]], 16
48; MM: wsbh $[[R0:[0-9]+]]
49; MM: rotr ${{[0-9]+}}, $[[R0]], 16
50
51; MIPS64-LABEL: bswap64:
52; MIPS64: dsbh $[[R0:[0-9]+]]
53; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
54
55; MIPS16-LABEL: bswap64:
56; MIPS16-DAG: srl $[[R0:[0-9]+]], $5, 8
57; MIPS16-DAG: srl $[[R1:[0-9]+]], $5, 24
58; MIPS16-DAG: sll $[[R2:[0-9]+]], $5, 8
59; MIPS16-DAG: sll $[[R3:[0-9]+]], $5, 24
60; MIPS16-DAG: li  $[[R4:[0-9]+]], 65280
61; MIPS16-DAG: and $[[R0]], $[[R4]]
62; MIPS16-DAG: or  $[[R1]], $[[R0]]
63; MIPS16-DAG: lw  $[[R7:[0-9]+]], 1f
64; MIPS16-DAG: and $[[R2]], $[[R7]]
65; MIPS16-DAG: or  $[[R3]], $[[R2]]
66; MIPS16-DAG: or  $[[R3]], $[[R1]]
67; MIPS16-DAG: srl $[[R0:[0-9]+]], $4, 8
68; MIPS16-DAG: srl $[[R1:[0-9]+]], $4, 24
69; MIPS16-DAG: sll $[[R2:[0-9]+]], $4, 8
70; MIPS16-DAG: sll $[[R3:[0-9]+]], $4, 24
71; MIPS16-DAG: li  $[[R4:[0-9]+]], 65280
72; MIPS16-DAG: and $[[R0]], $[[R4]]
73; MIPS16-DAG: or  $[[R1]], $[[R0]]
74; MIPS16-DAG: lw  $[[R7:[0-9]+]], 1f
75; MIPS16-DAG: and $[[R2]], $[[R7]]
76; MIPS16-DAG: or  $[[R3]], $[[R2]]
77; MIPS16-DAG: or  $[[R3]], $[[R1]]
78
79  %or.7 = call i64 @llvm.bswap.i64(i64 %x)
80  ret i64 %or.7
81}
82
83define <4 x i32> @bswapv4i32(<4 x i32> %x) nounwind readnone {
84entry:
85; MIPS32-LABEL: bswapv4i32:
86; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
87; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
88; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
89; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
90; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
91; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
92; MIPS32-DAG: wsbh $[[R0:[0-9]+]]
93; MIPS32-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
94
95; MM-LABEL: bswapv4i32:
96; MM-DAG: wsbh $[[R0:[0-9]+]]
97; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
98; MM-DAG: wsbh $[[R0:[0-9]+]]
99; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
100; MM-DAG: wsbh $[[R0:[0-9]+]]
101; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
102; MM-DAG: wsbh $[[R0:[0-9]+]]
103; MM-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
104
105; MIPS64-LABEL: bswapv4i32:
106; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
107; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
108; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
109; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
110; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
111; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
112; MIPS64-DAG: wsbh $[[R0:[0-9]+]]
113; MIPS64-DAG: rotr ${{[0-9]+}}, $[[R0]], 16
114
115; Don't bother with a MIPS16 version. It's just bswap32 repeated four times and
116; would be very long
117
118  %ret = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %x)
119  ret <4 x i32> %ret
120}
121
122declare i32 @llvm.bswap.i32(i32) nounwind readnone
123
124declare i64 @llvm.bswap.i64(i64) nounwind readnone
125
126declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>) nounwind readnone
127