1; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s 2; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \ 3; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING 4; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s 5; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \ 6; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING 7 8; bnezc and beqzc have restriction that $rt != 0 9 10define i32 @f() { 11; CHECK-LABEL: f: 12; CHECK-NOT: bnezc $0 13 14 %cmp = icmp eq i32 1, 1 15 br i1 %cmp, label %if.then, label %if.end 16 17 if.then: 18 ret i32 1 19 20 if.end: 21 ret i32 0 22} 23 24define i32 @f1() { 25; CHECK-LABEL: f1: 26; CHECK-NOT: beqzc $0 27 28 %cmp = icmp eq i32 0, 0 29 br i1 %cmp, label %if.then, label %if.end 30 31 if.then: 32 ret i32 1 33 34 if.end: 35 ret i32 0 36} 37 38; We silently fixup cases where the register allocator or user has given us 39; an instruction with incorrect operands that is trivially acceptable. 40; beqc and bnec have the restriction that $rs < $rt. 41 42define i32 @f2(i32 %a, i32 %b) { 43; ENCODING-LABEL: f2: 44; ENCODING-NOT: beqc $5, $4 45; ENCODING-NOT: bnec $5, $4 46 47 %cmp = icmp eq i32 %b, %a 48 br i1 %cmp, label %if.then, label %if.end 49 50 if.then: 51 ret i32 1 52 53 if.end: 54 ret i32 0 55} 56 57define i64 @f3() { 58; CHECK-LABEL: f3: 59; CHECK-NOT: bnezc $0 60 61 %cmp = icmp eq i64 1, 1 62 br i1 %cmp, label %if.then, label %if.end 63 64 if.then: 65 ret i64 1 66 67 if.end: 68 ret i64 0 69} 70 71define i64 @f4() { 72; CHECK-LABEL: f4: 73; CHECK-NOT: beqzc $0 74 75 %cmp = icmp eq i64 0, 0 76 br i1 %cmp, label %if.then, label %if.end 77 78 if.then: 79 ret i64 1 80 81 if.end: 82 ret i64 0 83} 84 85; We silently fixup cases where the register allocator or user has given us 86; an instruction with incorrect operands that is trivially acceptable. 87; beqc and bnec have the restriction that $rs < $rt. 88 89define i64 @f5(i64 %a, i64 %b) { 90; ENCODING-LABEL: f5: 91; ENCODING-NOT: beqc $5, $4 92; ENCODING-NOT: bnec $5, $4 93 94 %cmp = icmp eq i64 %b, %a 95 br i1 %cmp, label %if.then, label %if.end 96 97 if.then: 98 ret i64 1 99 100 if.end: 101 ret i64 0 102} 103 104define i32 @f6(i32 %a) { 105; CHECK-LABEL: f6: 106; CHECK: beqzc ${{[0-9]+}}, $BB 107 108 %cmp = icmp eq i32 %a, 0 109 br i1 %cmp, label %if.then, label %if.end 110 111 if.then: 112 ret i32 1 113 114 if.end: 115 ret i32 0 116} 117 118define i32 @f7(i32 %a) { 119; CHECK-LABEL: f7: 120; CHECK: bnezc ${{[0-9]+}}, $BB 121 122 %cmp = icmp eq i32 0, %a 123 br i1 %cmp, label %if.then, label %if.end 124 125 if.then: 126 ret i32 1 127 128 if.end: 129 ret i32 0 130} 131