1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5define void @foo(i32 %a, i32 *%b, i1 %c) {
6; RV32I-LABEL: foo:
7; RV32I:       # %bb.0:
8; RV32I-NEXT:    lw a3, 0(a1)
9; RV32I-NEXT:    beq a3, a0, .LBB0_12
10; RV32I-NEXT:  # %bb.1: # %test2
11; RV32I-NEXT:    lw a3, 0(a1)
12; RV32I-NEXT:    bne a3, a0, .LBB0_12
13; RV32I-NEXT:  # %bb.2: # %test3
14; RV32I-NEXT:    lw a3, 0(a1)
15; RV32I-NEXT:    blt a3, a0, .LBB0_12
16; RV32I-NEXT:  # %bb.3: # %test4
17; RV32I-NEXT:    lw a3, 0(a1)
18; RV32I-NEXT:    bge a3, a0, .LBB0_12
19; RV32I-NEXT:  # %bb.4: # %test5
20; RV32I-NEXT:    lw a3, 0(a1)
21; RV32I-NEXT:    bltu a3, a0, .LBB0_12
22; RV32I-NEXT:  # %bb.5: # %test6
23; RV32I-NEXT:    lw a3, 0(a1)
24; RV32I-NEXT:    bgeu a3, a0, .LBB0_12
25; RV32I-NEXT:  # %bb.6: # %test7
26; RV32I-NEXT:    lw a3, 0(a1)
27; RV32I-NEXT:    blt a0, a3, .LBB0_12
28; RV32I-NEXT:  # %bb.7: # %test8
29; RV32I-NEXT:    lw a3, 0(a1)
30; RV32I-NEXT:    bge a0, a3, .LBB0_12
31; RV32I-NEXT:  # %bb.8: # %test9
32; RV32I-NEXT:    lw a3, 0(a1)
33; RV32I-NEXT:    bltu a0, a3, .LBB0_12
34; RV32I-NEXT:  # %bb.9: # %test10
35; RV32I-NEXT:    lw a3, 0(a1)
36; RV32I-NEXT:    bgeu a0, a3, .LBB0_12
37; RV32I-NEXT:  # %bb.10: # %test11
38; RV32I-NEXT:    lw a0, 0(a1)
39; RV32I-NEXT:    andi a0, a2, 1
40; RV32I-NEXT:    bnez a0, .LBB0_12
41; RV32I-NEXT:  # %bb.11: # %test12
42; RV32I-NEXT:    lw a0, 0(a1)
43; RV32I-NEXT:  .LBB0_12: # %end
44; RV32I-NEXT:    ret
45  %val1 = load volatile i32, i32* %b
46  %tst1 = icmp eq i32 %val1, %a
47  br i1 %tst1, label %end, label %test2
48
49test2:
50  %val2 = load volatile i32, i32* %b
51  %tst2 = icmp ne i32 %val2, %a
52  br i1 %tst2, label %end, label %test3
53
54test3:
55  %val3 = load volatile i32, i32* %b
56  %tst3 = icmp slt i32 %val3, %a
57  br i1 %tst3, label %end, label %test4
58
59test4:
60  %val4 = load volatile i32, i32* %b
61  %tst4 = icmp sge i32 %val4, %a
62  br i1 %tst4, label %end, label %test5
63
64test5:
65  %val5 = load volatile i32, i32* %b
66  %tst5 = icmp ult i32 %val5, %a
67  br i1 %tst5, label %end, label %test6
68
69test6:
70  %val6 = load volatile i32, i32* %b
71  %tst6 = icmp uge i32 %val6, %a
72  br i1 %tst6, label %end, label %test7
73
74; Check for condition codes that don't have a matching instruction
75
76test7:
77  %val7 = load volatile i32, i32* %b
78  %tst7 = icmp sgt i32 %val7, %a
79  br i1 %tst7, label %end, label %test8
80
81test8:
82  %val8 = load volatile i32, i32* %b
83  %tst8 = icmp sle i32 %val8, %a
84  br i1 %tst8, label %end, label %test9
85
86test9:
87  %val9 = load volatile i32, i32* %b
88  %tst9 = icmp ugt i32 %val9, %a
89  br i1 %tst9, label %end, label %test10
90
91test10:
92  %val10 = load volatile i32, i32* %b
93  %tst10 = icmp ule i32 %val10, %a
94  br i1 %tst10, label %end, label %test11
95
96; Check the case of a branch where the condition was generated in another
97; function
98
99test11:
100  %val11 = load volatile i32, i32* %b
101  br i1 %c, label %end, label %test12
102
103test12:
104  %val12 = load volatile i32, i32* %b
105  br label %end
106
107end:
108  ret void
109}
110