1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IFD %s
4
5define double @double_imm() nounwind {
6; RV32IFD-LABEL: double_imm:
7; RV32IFD:       # %bb.0:
8; RV32IFD-NEXT:    addi sp, sp, -16
9; RV32IFD-NEXT:    lui a0, %hi(.LCPI0_0)
10; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI0_0)
11; RV32IFD-NEXT:    fld ft0, 0(a0)
12; RV32IFD-NEXT:    fsd ft0, 8(sp)
13; RV32IFD-NEXT:    lw a0, 8(sp)
14; RV32IFD-NEXT:    lw a1, 12(sp)
15; RV32IFD-NEXT:    addi sp, sp, 16
16; RV32IFD-NEXT:    ret
17  ret double 3.1415926535897931159979634685441851615905761718750
18}
19
20define double @double_imm_op(double %a) nounwind {
21; RV32IFD-LABEL: double_imm_op:
22; RV32IFD:       # %bb.0:
23; RV32IFD-NEXT:    addi sp, sp, -16
24; RV32IFD-NEXT:    sw a0, 8(sp)
25; RV32IFD-NEXT:    sw a1, 12(sp)
26; RV32IFD-NEXT:    fld ft0, 8(sp)
27; RV32IFD-NEXT:    lui a0, %hi(.LCPI1_0)
28; RV32IFD-NEXT:    addi a0, a0, %lo(.LCPI1_0)
29; RV32IFD-NEXT:    fld ft1, 0(a0)
30; RV32IFD-NEXT:    fadd.d ft0, ft0, ft1
31; RV32IFD-NEXT:    fsd ft0, 8(sp)
32; RV32IFD-NEXT:    lw a0, 8(sp)
33; RV32IFD-NEXT:    lw a1, 12(sp)
34; RV32IFD-NEXT:    addi sp, sp, 16
35; RV32IFD-NEXT:    ret
36  %1 = fadd double %a, 1.0
37  ret double %1
38}
39