1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32IF %s
4
5define i32 @fcvt_w_s(float %a) nounwind {
6; RV32IF-LABEL: fcvt_w_s:
7; RV32IF:       # %bb.0:
8; RV32IF-NEXT:    fmv.w.x ft0, a0
9; RV32IF-NEXT:    fcvt.w.s a0, ft0, rtz
10; RV32IF-NEXT:    ret
11  %1 = fptosi float %a to i32
12  ret i32 %1
13}
14
15define i32 @fcvt_wu_s(float %a) nounwind {
16; RV32IF-LABEL: fcvt_wu_s:
17; RV32IF:       # %bb.0:
18; RV32IF-NEXT:    fmv.w.x ft0, a0
19; RV32IF-NEXT:    fcvt.wu.s a0, ft0, rtz
20; RV32IF-NEXT:    ret
21  %1 = fptoui float %a to i32
22  ret i32 %1
23}
24
25define i32 @fmv_x_w(float %a, float %b) nounwind {
26; RV32IF-LABEL: fmv_x_w:
27; RV32IF:       # %bb.0:
28; RV32IF-NEXT:    fmv.w.x ft0, a1
29; RV32IF-NEXT:    fmv.w.x ft1, a0
30; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
31; RV32IF-NEXT:    fmv.x.w a0, ft0
32; RV32IF-NEXT:    ret
33; Ensure fmv.x.w is generated even for a soft float calling convention
34  %1 = fadd float %a, %b
35  %2 = bitcast float %1 to i32
36  ret i32 %2
37}
38
39define float @fcvt_s_w(i32 %a) nounwind {
40; RV32IF-LABEL: fcvt_s_w:
41; RV32IF:       # %bb.0:
42; RV32IF-NEXT:    fcvt.s.w ft0, a0
43; RV32IF-NEXT:    fmv.x.w a0, ft0
44; RV32IF-NEXT:    ret
45  %1 = sitofp i32 %a to float
46  ret float %1
47}
48
49define float @fcvt_s_wu(i32 %a) nounwind {
50; RV32IF-LABEL: fcvt_s_wu:
51; RV32IF:       # %bb.0:
52; RV32IF-NEXT:    fcvt.s.wu ft0, a0
53; RV32IF-NEXT:    fmv.x.w a0, ft0
54; RV32IF-NEXT:    ret
55  %1 = uitofp i32 %a to float
56  ret float %1
57}
58
59define float @fmv_w_x(i32 %a, i32 %b) nounwind {
60; RV32IF-LABEL: fmv_w_x:
61; RV32IF:       # %bb.0:
62; RV32IF-NEXT:    fmv.w.x ft0, a1
63; RV32IF-NEXT:    fmv.w.x ft1, a0
64; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
65; RV32IF-NEXT:    fmv.x.w a0, ft0
66; RV32IF-NEXT:    ret
67; Ensure fmv.w.x is generated even for a soft float calling convention
68  %1 = bitcast i32 %a to float
69  %2 = bitcast i32 %b to float
70  %3 = fadd float %1, %2
71  ret float %3
72}
73