1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck %s -check-prefix=RV32I
4
5; Basic shift support is tested as part of ALU.ll. This file ensures that
6; shifts which may not be supported natively are lowered properly.
7
8define i64 @lshr64(i64 %a, i64 %b) nounwind {
9; RV32I-LABEL: lshr64:
10; RV32I:       # %bb.0:
11; RV32I-NEXT:    addi sp, sp, -16
12; RV32I-NEXT:    sw ra, 12(sp)
13; RV32I-NEXT:    call __lshrdi3
14; RV32I-NEXT:    lw ra, 12(sp)
15; RV32I-NEXT:    addi sp, sp, 16
16; RV32I-NEXT:    ret
17  %1 = lshr i64 %a, %b
18  ret i64 %1
19}
20
21define i64 @ashr64(i64 %a, i64 %b) nounwind {
22; RV32I-LABEL: ashr64:
23; RV32I:       # %bb.0:
24; RV32I-NEXT:    addi sp, sp, -16
25; RV32I-NEXT:    sw ra, 12(sp)
26; RV32I-NEXT:    call __ashrdi3
27; RV32I-NEXT:    lw ra, 12(sp)
28; RV32I-NEXT:    addi sp, sp, 16
29; RV32I-NEXT:    ret
30  %1 = ashr i64 %a, %b
31  ret i64 %1
32}
33
34define i64 @shl64(i64 %a, i64 %b) nounwind {
35; RV32I-LABEL: shl64:
36; RV32I:       # %bb.0:
37; RV32I-NEXT:    addi sp, sp, -16
38; RV32I-NEXT:    sw ra, 12(sp)
39; RV32I-NEXT:    call __ashldi3
40; RV32I-NEXT:    lw ra, 12(sp)
41; RV32I-NEXT:    addi sp, sp, 16
42; RV32I-NEXT:    ret
43  %1 = shl i64 %a, %b
44  ret i64 %1
45}
46