1; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8
2; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9
3; RUN: llc -mtriple=sparc64-unknown-linux <%s | FileCheck %s -check-prefix=SPARC64
4
5
6define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline {
7entry:
8; V8: addcc
9; V8-NOT: subcc
10; V8: addx
11; V9: addcc
12; V9-NOT: subcc
13; V9: addx
14; V9: mov{{e|ne}} %icc
15  %0 = add i64 %a, %b
16  %1 = icmp ugt i64 %0, %c
17  %2 = zext i1 %1 to i32
18  ret i32 %2
19}
20
21
22define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline {
23entry:
24; V8: test_select_int_icc
25; V8: cmp
26; V8: {{be|bne}}
27; V9: test_select_int_icc
28; V9: cmp
29; V9-NOT: {{be|bne}}
30; V9: mov{{e|ne}} %icc
31  %0 = icmp eq i32 %a, 0
32  %1 = select i1 %0, i32 %b, i32 %c
33  ret i32 %1
34}
35
36
37define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline {
38entry:
39; V8: test_select_fp_icc
40; V8: cmp
41; V8: {{be|bne}}
42; V9: test_select_fp_icc
43; V9: cmp
44; V9-NOT: {{be|bne}}
45; V9: fmovs{{e|ne}} %icc
46  %0 = icmp eq i32 %a, 0
47  %1 = select i1 %0, float %f1, float %f2
48  ret float %1
49}
50
51define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline {
52entry:
53; V8: test_select_dfp_icc
54; V8: cmp
55; V8: {{be|bne}}
56; V9: test_select_dfp_icc
57; V9: cmp
58; V9-NOT: {{be|bne}}
59; V9: fmovd{{e|ne}} %icc
60  %0 = icmp eq i32 %a, 0
61  %1 = select i1 %0, double %f1, double %f2
62  ret double %1
63}
64
65define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline {
66entry:
67;V8-LABEL: test_select_int_fcc:
68;V8: fcmps
69;V8-NEXT: nop
70;V8: {{fbe|fbne}}
71;V9-LABEL: test_select_int_fcc:
72;V9: fcmps
73;V9-NOT: nop
74;V9-NOT: {{fbe|fbne}}
75;V9: mov{{e|ne}} %fcc0
76  %0 = fcmp une float %f, 0.000000e+00
77  %a.b = select i1 %0, i32 %a, i32 %b
78  ret i32 %a.b
79}
80
81
82define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline {
83entry:
84;V8-LABEL: test_select_fp_fcc:
85;V8: fcmps
86;V8: {{fbe|fbne}}
87;V9-LABEL: test_select_fp_fcc:
88;V9: fcmps
89;V9-NOT: {{fbe|fbne}}
90;V9: fmovs{{e|ne}} %fcc0
91  %0 = fcmp une float %f, 0.000000e+00
92  %1 = select i1 %0, float %f1, float %f2
93  ret float %1
94}
95
96define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline {
97entry:
98;V8-LABEL: test_select_dfp_fcc:
99;V8: fcmpd
100;V8-NEXT: nop
101;V8: {{fbne|fbe}}
102;V9-LABEL: test_select_dfp_fcc:
103;V9: fcmpd
104;V9-NOT: nop
105;V9-NOT: {{fbne|fbe}}
106;V9: fmovd{{e|ne}} %fcc0
107  %0 = fcmp une double %f, 0.000000e+00
108  %1 = select i1 %0, double %f1, double %f2
109  ret double %1
110}
111
112define i32 @test_float_cc(double %a, double %b, i32 %c, i32 %d) {
113entry:
114; V8-LABEL: test_float_cc
115; V8:       fcmpd
116; V8:       {{fbl|fbuge}} .LBB
117; V8:       fcmpd
118; V8:       {{fbule|fbg}} .LBB
119
120; V9-LABEL: test_float_cc
121; V9:       fcmpd
122; V9:       {{fbl|fbuge}} .LBB
123; V9:       fcmpd
124; V9:       {{fbule|fbg}} .LBB
125
126   %0 = fcmp uge double %a, 0.000000e+00
127   br i1 %0, label %loop, label %loop.2
128
129loop:
130   %1 = icmp eq i32 %c, 10
131   br i1 %1, label %loop, label %exit.0
132
133loop.2:
134   %2 = fcmp ogt double %b, 0.000000e+00
135   br i1 %2, label %exit.1, label %loop
136
137exit.0:
138   ret i32 0
139
140exit.1:
141   ret i32 1
142}
143
144; V8-LABEL: test_adde_sube
145; V8:       addcc
146; V8:       addxcc
147; V8:       addxcc
148; V8:       addxcc
149; V8:       subcc
150; V8:       subxcc
151; V8:       subxcc
152; V8:       subxcc
153
154
155; V9-LABEL: test_adde_sube
156; V9:       addcc
157; V9:       addxcc
158; V9:       addxcc
159; V9:       addxcc
160; V9:       subcc
161; V9:       subxcc
162; V9:       subxcc
163; V9:       subxcc
164
165; SPARC64-LABEL: test_adde_sube
166; SPARC64:       addcc
167; SPARC64:       addxcc
168; SPARC64:       addxcc
169; SPARC64:       addxcc
170; SPARC64:       subcc
171; SPARC64:       subxcc
172; SPARC64:       subxcc
173; SPARC64:       subxcc
174
175
176define void @test_adde_sube(i8* %a, i8* %b, i8* %sum, i8* %diff) {
177entry:
178   %0 = bitcast i8* %a to i128*
179   %1 = bitcast i8* %b to i128*
180   %2 = load i128, i128* %0
181   %3 = load i128, i128* %1
182   %4 = add i128 %2, %3
183   %5 = bitcast i8* %sum to i128*
184   store i128 %4, i128* %5
185   tail call void asm sideeffect "", "=*m,*m"(i128 *%0, i128* %5) nounwind
186   %6 = load i128, i128* %0
187   %7 = sub i128 %2, %6
188   %8 = bitcast i8* %diff to i128*
189   store i128 %7, i128* %8
190   ret void
191}
192