1; Test vector subtraction.
2;
3; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
4
5; Test a v16i8 subtraction.
6define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) {
7; CHECK-LABEL: f1:
8; CHECK: vsb %v24, %v26, %v28
9; CHECK: br %r14
10  %ret = sub <16 x i8> %val1, %val2
11  ret <16 x i8> %ret
12}
13
14; Test a v8i16 subtraction.
15define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) {
16; CHECK-LABEL: f2:
17; CHECK: vsh %v24, %v26, %v28
18; CHECK: br %r14
19  %ret = sub <8 x i16> %val1, %val2
20  ret <8 x i16> %ret
21}
22
23; Test a v4i32 subtraction.
24define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) {
25; CHECK-LABEL: f3:
26; CHECK: vsf %v24, %v26, %v28
27; CHECK: br %r14
28  %ret = sub <4 x i32> %val1, %val2
29  ret <4 x i32> %ret
30}
31
32; Test a v2i64 subtraction.
33define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) {
34; CHECK-LABEL: f4:
35; CHECK: vsg %v24, %v26, %v28
36; CHECK: br %r14
37  %ret = sub <2 x i64> %val1, %val2
38  ret <2 x i64> %ret
39}
40
41; Test a v4f32 subtraction, as an example of an operation that needs to be
42; scalarized and reassembled.  At present there's an unnecessary move that
43; could be avoided with smarter ordering.  It also isn't important whether
44; the VSLDBs use the result of the VLRs or use %v24 and %v26 directly.
45define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) {
46; CHECK-LABEL: f5:
47; CHECK-DAG: vlr %v[[A1:[0-5]]], %v24
48; CHECK-DAG: vlr %v[[A2:[0-5]]], %v26
49; CHECK-DAG: vrepf %v[[B1:[0-5]]], %v24, 1
50; CHECK-DAG: vrepf %v[[B2:[0-5]]], %v26, 1
51; CHECK-DAG: vrepf %v[[C1:[0-5]]], %v24, 2
52; CHECK-DAG: vrepf %v[[C2:[0-5]]], %v26, 2
53; CHECK-DAG: vrepf %v[[D1:[0-5]]], %v24, 3
54; CHECK-DAG: vrepf %v[[D2:[0-5]]], %v26, 3
55; CHECK-DAG: sebr %f[[A1]], %f[[A2]]
56; CHECK-DAG: sebr %f[[B1]], %f[[B2]]
57; CHECK-DAG: sebr %f[[C1]], %f[[C2]]
58; CHECK-DAG: sebr %f[[D1]], %f[[D2]]
59; CHECK-DAG: vmrhf [[HIGH:%v[0-9]+]], %v[[A1]], %v[[B1]]
60; CHECK-DAG: vmrhf [[LOW:%v[0-9]+]], %v[[C1]], %v[[D1]]
61; CHECK: vmrhg %v24, [[HIGH]], [[LOW]]
62; CHECK: br %r14
63  %ret = fsub <4 x float> %val1, %val2
64  ret <4 x float> %ret
65}
66
67; Test a v2f64 subtraction.
68define <2 x double> @f6(<2 x double> %dummy, <2 x double> %val1,
69                        <2 x double> %val2) {
70; CHECK-LABEL: f6:
71; CHECK: vfsdb %v24, %v26, %v28
72; CHECK: br %r14
73  %ret = fsub <2 x double> %val1, %val2
74  ret <2 x double> %ret
75}
76
77; Test an f64 subtraction that uses vector registers.
78define double @f7(<2 x double> %val1, <2 x double> %val2) {
79; CHECK-LABEL: f7:
80; CHECK: wfsdb %f0, %v24, %v26
81; CHECK: br %r14
82  %scalar1 = extractelement <2 x double> %val1, i32 0
83  %scalar2 = extractelement <2 x double> %val2, i32 0
84  %ret = fsub double %scalar1, %scalar2
85  ret double %ret
86}
87
88; Test a v2i8 subtraction, which gets promoted to v16i8.
89define <2 x i8> @f8(<2 x i8> %dummy, <2 x i8> %val1, <2 x i8> %val2) {
90; CHECK-LABEL: f8:
91; CHECK: vsb %v24, %v26, %v28
92; CHECK: br %r14
93  %ret = sub <2 x i8> %val1, %val2
94  ret <2 x i8> %ret
95}
96
97; Test a v4i8 subtraction, which gets promoted to v16i8.
98define <4 x i8> @f9(<4 x i8> %dummy, <4 x i8> %val1, <4 x i8> %val2) {
99; CHECK-LABEL: f9:
100; CHECK: vsb %v24, %v26, %v28
101; CHECK: br %r14
102  %ret = sub <4 x i8> %val1, %val2
103  ret <4 x i8> %ret
104}
105
106; Test a v8i8 subtraction, which gets promoted to v16i8.
107define <8 x i8> @f10(<8 x i8> %dummy, <8 x i8> %val1, <8 x i8> %val2) {
108; CHECK-LABEL: f10:
109; CHECK: vsb %v24, %v26, %v28
110; CHECK: br %r14
111  %ret = sub <8 x i8> %val1, %val2
112  ret <8 x i8> %ret
113}
114
115; Test a v2i16 subtraction, which gets promoted to v8i16.
116define <2 x i16> @f11(<2 x i16> %dummy, <2 x i16> %val1, <2 x i16> %val2) {
117; CHECK-LABEL: f11:
118; CHECK: vsh %v24, %v26, %v28
119; CHECK: br %r14
120  %ret = sub <2 x i16> %val1, %val2
121  ret <2 x i16> %ret
122}
123
124; Test a v4i16 subtraction, which gets promoted to v8i16.
125define <4 x i16> @f12(<4 x i16> %dummy, <4 x i16> %val1, <4 x i16> %val2) {
126; CHECK-LABEL: f12:
127; CHECK: vsh %v24, %v26, %v28
128; CHECK: br %r14
129  %ret = sub <4 x i16> %val1, %val2
130  ret <4 x i16> %ret
131}
132
133; Test a v2i32 subtraction, which gets promoted to v4i32.
134define <2 x i32> @f13(<2 x i32> %dummy, <2 x i32> %val1, <2 x i32> %val2) {
135; CHECK-LABEL: f13:
136; CHECK: vsf %v24, %v26, %v28
137; CHECK: br %r14
138  %ret = sub <2 x i32> %val1, %val2
139  ret <2 x i32> %ret
140}
141
142; Test a v2f32 subtraction, which gets promoted to v4f32.
143define <2 x float> @f14(<2 x float> %val1, <2 x float> %val2) {
144; No particular output expected, but must compile.
145  %ret = fsub <2 x float> %val1, %val2
146  ret <2 x float> %ret
147}
148